International Business Machines Corporation

Ryan Charles Kivimagi

Derick Gardner Behrends

Chad Allen Adams

Peter Thomas Freiburger

Todd Alan Christensen

Anthony Gus Aipperspach

Daniel Mark Nelson

Chihhung Liao

Robert N Krentler

In some aspects, an apparatus is provided. The apparatus includes a plurality of memory arrays, a latch, and a selection circuit coupled to the plurality of memory arrays and to the latch. The selection circuit may be operative to receive a bit from each of a plurality of memory arrays select one of the plurality of memory arrays, and store the bit from the selected memory array. Numerous other aspects are provided.

Methods and apparatus for testing integrated circuits

A method and enhanced Static Random Access Memory (SRAM) redundancy circuit reduce wiring and the required number of redundant elements. A bitline redundancy mechanism allows the swapping of a pair of bitlines for a redundant pair of bit columns. Two of the adjacent bitlines are swapped out at a time, one even and one odd. The swap is accomplished by steering the data around the bad columns and adding redundant columns on the end that are steered in when needed.

Method for reducing wiring and required number of redundant elements

In some aspects a method is provided for testing an integrated circuit (IC). The method includes the steps of selecting a bit from each of a plurality of memory arrays formed on an IC chip, selecting one of the plurality of memory arrays, and storing the selected bit from the selected memory array. Numerous other aspects are provided.

A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood mode is induced by beginning with a normal write operation. After new data values have been forced into the SRAM cells, then the write signal is chopped off. A delay block keeps the wordline signal at the high supply, and the SRAM cells go into flood mode. At this juncture marginal cells can be easily detected and later mapped to redundant cells.

Flood mode implementation for continuous bitline local evaluation circuit

A glitch protect valid cell and method for maintaining a desired logic state value. The glitch protect valid cell includes a memory element, a state machine, and a glitch protect circuit. The glitch protect circuit includes a propagation delay assembly coupled to a restore assembly. The propagation delay assembly includes a first pull down network coupled to a NOR gate. The restore assembly includes a second pull down network coupled to the propagation delay assembly. Responsive to a glitch signal and timing signal, the first pull down network resets the initial state value of a true valid bit to ultimately enable a pull up network in the NOR gate. Responsive to enablement of the NOR gate pull up network, the second pull down network resets the complement valid bit in the memory element to consequently restore the initial state of the true valid bit.

Glitch protect valid cell and method for maintaining a desired state value

An apparatus and method provide logically controlled masking of one or more maskable data bits from a plurality of data bits that are input to a dynamic logic circuit. No masking logic and attendant delay penalty is coupled in the data path that is not needed for unmasked bits from the plurality of data bits that do not need masking. A system clock has a precharge phase and an evaluate phase. A first clock buffer is coupled to a precharge switch and precharges a dynamic node during the precharge phase. A second clock buffer having substantially the same delay from system clock input to an output of the second clock buffer is gated by a derivative of a mask. The output of the second clock buffer controls one or more switches in series with switches controlled by the maskable data bits.

Maskable dynamic logic

A method and a sum addressed content-addressable memory (CAM) compare are provided for implementing an enhanced sum address compare function. True and compliment bit signals applied to the CAM compare are encoded by combining respective ones of the applied true and compliment bit signals. Then the encoded true and compliment bit signals are applied to a critical path dynamic compare circuit. An encoder apparatus encodes true and compliment bit signals that then are applied to the dynamic compare circuit in the critical path.

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Chatfield, MN, United States of America

Ryan Charles Kivimagi