Intel Corporation

Ryan Carlson

Matthew C Merten

Anupama Suryanarayanan

Stephen H Gunther

Robert S Chappell

Nagi Aboulenein

Hemant G Rotithor

Omar M Shaikh

Ravishankar Iyer

Raanan Sade

Stanislav Shwartsman

Ronak Singhal

Li Zhao

Paul Caprioli

Zhen Fang

Ramacharan Sundararaman

Gustavo P Espinosa

Ho-Seop Kim

Puqi Perry Tang

Liron Zur

Jianwei Dai

Muawya M Al-Otoom

Yiftach Gilad

Perry P Tang

Meenakshisundara R Chinthamani

Milind B Kamble

Seung Eun Lee

JunSeong Kim

In an embodiment, a data path circuit includes: a plurality of pipeline stages coupled between an input of the data path circuit and an output of the data path circuit; and a first selection circuit coupled between a first pipeline stage and a second pipeline stage, the first selection circuit having a first input to receive an input to the first pipeline stage and a second input to receive an output of the first pipeline stage and controllable to output one of the input to the first pipeline stage and the output of the first pipeline stage. A bypass controller coupled to the data path circuit may control the first selection circuit based at least in part on an operating frequency of the data path circuit. Other embodiments are described and claimed.

System, apparatus and method for dynamic pipeline stage control of data path dominant circuitry of an integrated circuit

Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.

Method, apparatus, and system for energy efficiency and energy conservation including detecting and controlling current ramps in processing circuit

In an embodiment, a processor includes at least one core including a first core. The first core includes memory execution logic to execute one or more memory instructions, memory dispatch logic to output a plurality of memory instructions to the memory execution logic, and reactive memory instruction tracking logic. The reactive memory instruction tracking logic is to detect an onset of a memory instruction high power event associated with execution of at least one of the memory instructions, and to indicate to the memory dispatch logic to throttle output of the memory instructions to the memory execution logic responsive to detection of the onset of the memory instruction high power event. The processor also includes cache memory coupled to the at least one core. Other embodiments are described and claimed.

Method and apparatus to prevent voltage droop in a computer

A processor includes a cache hierarchy and an execution unit. The cache hierarchy includes a lower level cache and a higher level cache. The execution unit includes logic to issue a memory operation to access the cache hierarchy. The lower level cache includes logic to determine that a requested cache line of the memory operation is unavailable in the lower level cache, determine that a line fill buffer of the lower level cache is full, and initiate prefetching of the requested cache line from the higher level cache based upon the determination that the line fill buffer of the lower level cache is full. The line fill buffer is to forward miss requests to the higher level cache.

Instruction and logic for a cache prefetcher and dataless fill buffer

Method and apparatus to efficiently detect violations of data dependency relationships. A memory address associated with a computer instruction may be obtained. A current state of the memory address may be identified. The current state may include whether the memory address is associated with a read or a store instruction, and whether the memory address is associated with a set or a check. A previously accumulated state associated with the memory address may be retrieved from a data structure. The previously accumulated state may include whether the memory address was previously associated with a read or a store instruction, and whether the memory address was previously associated with a set or a check. If a transition from the previously accumulated state to the current state is invalid, a failure condition may be signaled.

Detection of memory address aliasing and violations of data dependency relationships

An apparatus and method is described herein for optimization to prefetch throttling, which potentially enhances performance, reduces power consumption, and maintains positive gain for workloads that benefit from prefetching. More specifically, the optimizations described herein allow for bandwidth congestion and prefetch accuracy to be taken into account as feedbacks for throttling at the source of prefetch generation. As a result, when there is low congestion, full prefetch generation is allowed, even if the prefetch is inaccurate, since there is available bandwidth. However, when congestion is high, the determination of throttling falls to prefetch accuracy. If accuracy is high&#x2014;miss rate is low&#x2014;then less throttling is needed, because the prefetches are being utilized&#x2014;performance is being enhanced. Yet, if prefetch accuracy is low&#x2014;miss rate is high&#x2014;then more prefetch throttling is needed to save power, because the prefetch are not being utilized&#x2014;performance is not being enhanced by the large number of prefetches.

Prefetch optimization in shared resource multi-core systems

Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.

Cache memory power reduction techniques

Mechanisms for improving the efficiency of bus-request scheduling are provided. In a read-write segregation mechanism the type of a selected entry in a buffer is determined. If the type of the selected entry matches the type of the last issued entry, or if there are no further entries in the buffer that match the last issued entry, the request is issued to the system bus. A temporal ordering mechanism associates a request sent to a buffer with an identifier, the identifier designating a time at which the request was originally generated. The request identifier is modified when a prior request is issued, and thereby reflects a history of prior issuances. A request is issued when the historical information recorded in the identifier indicates that the request is the earliest-issued pending request in the buffer. A third mechanism for increasing the efficiency of bus request scheduling in a buffer includes segregating lower priority cache eviction requests in a separate write-out section of the buffer. Request entries in the write-out section are issued to a system bus only when there are no pending entries in a bus queue.

System and method for optimizing memory bus bandwidth utilization by request classification and ordering

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Hillsboro, OR, United States of America

Ryan Carlson