Intermolecular, Inc.

Kabushiki Kaisha Toshiba

Sandisk 3d LLC

Ryan C Clarke

Yun Yu Wang

Imran Hashim

Yoram Schwarz

Tim Minvielle

Tony P Chiang

Takeshi Yamaguchi

Sandra Guy Malhotra

Sunil Shanker

Federico Nardi

Nan Lu

Chi-I Lang

Robert A Huertas

Vidyut Gopal

Randall Higuchi

A nonvolatile sample and hold circuit can include a resistive switching circuit, a sample circuit, a reset circuit, and a converter circuit. The resistive switching circuit can be operable to accept an input voltage Vg, and provide a resistance response Rrs that corresponds to the input signal Vg. The sampling circuit can be operable to sample an input signal such as an input voltage Vin, to provide a sampled voltage Vg. The reset circuit can be operable to reset the resistive switching circuit to a high resistance state. The converter circuit can be operable to convert the resistive switching circuit to an output voltage. The novel sample and hold circuit can have no issues related to charge injection, no settling time and instantaneous sampling time, together with potentially infinite hold time.

Resistive switching sample and hold

Provided are resistive random access memory (ReRAM) cells, each having three or more resistive states and being capable of storing multiple bits of data, as well as methods of fabricating and operating such ReRAM cells. Such ReRAM cells or, more specifically, their resistive switching layer have wide range of resistive states and are capable of being very conductive (e.g., about 1 kOhm) in one state and very resistive (e.g., about 1 MOhm) in another state. In some embodiments, a resistance ratio between resistive states may be between 10 and 1,000 even up to 10,000. The resistive switching layers also allow establishing stable and distinct intermediate resistive states that may be assigned different data values. These layers may be configured to switching between their resistive states using fewer programming pulses than conventional systems by using specific materials, switching pluses, and resistive state threshold.

Resistive random access memory cell having three or more resistive states

Provided are resistive random access memory (ReRAM) cells having extended conductive layers operable as electrodes of other devices, and methods of fabricating such cells and other devices. A conductive layer of a ReRAM cell extends beyond the cell boundary defined by the variable resistance layer. The extended portion may be used a source or drain region of a FET that may control an electrical current through the cell or other devices. The extended conductive layer may be also operable as electrode of another resistive-switching cell or a different device. The extended conductive layer may be formed from doped silicon. The variable resistance layer of the ReRAM cell may be positioned on the same level as a gate dielectric layer of the FET. The variable resistance layer and the gate dielectric layer may have the same thickness and share common materials, though they may be differently doped.

Resistive random access memory cells having shared electrodes with transistor devices

A combinatorial screening method and system are provided. The combinatorial system and method provide rapid data generation for characterization of phase change material. The characterization data is collected through a multipoint probe card where multiple regions are characterized in a single annealing cycle.

Combinatorial screening method and apparatus

Combinatorial screening methods and apparatus

A nonvolatile resistive memory element includes a host oxide formed from an interfacial oxide layer. The interfacial oxide layer is formed on the surface of a deposited electrode layer via in situ or post-deposition surface oxidation treatments.

Interfacial oxide used as switching layer in a nonvolatile resistive memory element

Method and apparatus for parallel testing of multiple regions on a substrate used in high performance combinatorial development of new materials and processes are described. The apparatus comprises dedicated hardware for each probe assembly with multiple PC controllers networked using a master/slave configuration.

Method and apparatus for parallel testing of semiconductor devices

A method and system of improved reliability testing includes providing a first substrate and a second substrate, each substrate comprising only a first metallization layer; processing regions on a first substrate by combinatorially varying at least one of materials, unit processes, and process sequences; performing a first reliability test on the processed regions on the first substrate to generate first results; processing regions on a second substrate in a combinatorial manner by varying at least one of materials, unit processes, and process sequences based on the first results of the first reliability test; performing a second reliability test on the processed regions on the second substrate to generate second results; and determining whether the first substrate and the second substrate meet a predetermined quality threshold based on the second results.

Method and system of improved reliability testing

A method for testing multiple coupons is described. The x, y, and theta offset coordinates of a reference structure for each coupon are determined. Additionally, the x and y offset coordinates between the reference structure and the first test device are determined. After the reference data from all of the coupons have been determined, the testing sequence for all of the coupons can be initiated and completed without further intervention.

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San Jose, CA, United States of America

Ryan C Clarke