Azurengine Technologies, Inc.

Azurengine Technologies Zhuhai Inc.

Ryan Braidwood

Yuan Li

Jianbin Zhu

Toshio Nagata

Processors, systems and methods are provided for thread level parallel processing. A processor may include a sequencer configured to: decode instructions that include scalar instructions and vector instructions, execute decoded scalar instructions, and package decoded vector instructions as configurations. The processor may further include a plurality of columns of vector processing units coupled to the sequencer. The plurality of columns of vector processing units may include a plurality of processing elements (PEs) and each of the PEs may include a plurality of Arithmetic Logic Units (ALUs). The sequencer may be configured to send the configurations to the plurality of columns of vector processing units.

Mixed scalar and vector operations in multi-threaded computing

A processor may include a plurality of columns of vector processing units arranged in a two-dimensional column array with a plurality of column stacks placed side-by-side in a first direction and each column stack having two columns stacked in a second direction. The processor may further include a memory unit divided into two portions placed on two opposite sides of the column array in the second direction. Each portion may contain two memory blocks placed side-by-side in the first direction. Each memory block may contain two cache blocks placed along a first edge abutting an adjacent memory block and a plurality banks of memory cells placed to space from the first edge in the first direction by the two cache blocks and from a second edge abutting the column array in the second direction by routing channels.

On-chip memory system for a reconfigurable parallel processor

Processors, systems and methods are provided for thread level parallel processing. A processor may include a plurality of columns of vector processing units arranged in a two-dimensional column array with a plurality of column stacks placed side-by-side in a first direction and each column stack having two columns stacked in a second direction and a temporary storage buffer. Each column may include a processing element (PE) that has a vector Arithmetic Logic Unit (ALU) to perform arithmetic operations in parallel threads. At a first end of the column array in the first direction, two columns in the column stack are coupled to the temporary storage buffer for one-way data flow. At a second end of the column array in the first direction, two columns are coupled to each other for one-way data flow. The column array and the temporary storage buffer may form a one-way circular data path.

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San Diego, CA, United States of America

Ryan Braidwood