Hewlett Packard Enterprise Development LP

Ryan Barnhill

Dacheng Zhou

Christopher Allan Poirier

Daniel Alan Berkram

Christopher B Wilson

Michael James Marshall

Peter Tsugio Kurahashi

A frontend circuit of a time-interleaved ADC is provided. The frontend circuit can include a track-and-hold circuit to sample an analog input signal to the ADC, a sub-ADC circuit to convert the sampled analog input signal to a digital output signal, and a source-follower circuit. An input of the source-follower circuit can be coupled to an output of the track-and-hold circuit, and an output of the source-follower circuit can be coupled to an input of the sub-ADC circuit. The source-follower circuit is to provide buffering between the track-and-hold circuit and the sub-ADC circuit. The circuit further includes a common-mode-adjusting circuit to dynamically adjust common-mode settings of the time-interleaved ADC. While adjusting the common-mode settings, the common-mode-adjusting circuit can adjust, separately, an input common-mode voltage of the track-and-hold circuit and an input common-mode voltage of the sub-ADC circuit based on current Process, Voltage, and Temperature (PVT) conditions.

Method and system for improving analog-to-digital conversion performance

Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.

Set-reset latches

One embodiment can provide a sampler for a decision feedback equalizer (DFE). The sampler can include a comparator comprising a resolver and a plurality of amplifiers coupled to the resolver. The plurality of amplifiers are to receive an input signal and one or more feedback signals, and the plurality of amplifiers are coupled to each other in parallel, thereby facilitating a summation of the input signal and the one or more feedback signals. The comparator is to generate an output based on the summation of the input signals and the one or more feedback signals. The sampler can further include an inverter to invert the output of the comparator. The inverted output of the inverter is sent to a tap-1 amplifier to generate a tap-1 feedback signal to be sent to the comparator at a next unit interval (UI).

Feedback circuit for a decision feedback equalizer

A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver.

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Fort Collins, CO, United States of America

Ryan Barnhill