Texas Instruments Corporation

Ryan Alexander Smith

Per Torstein Roine

Danielle Griffith

Abhijit Kumar Das

James N Murdock

Atul Ramakant Lele

Bernd Hannes Schneider

Viral Parikh

Paul John Patchen

An electronic circuit includes an oscillator circuit, a first divider circuit, a synchronization control circuit, and a peripheral circuit. The oscillator circuit is configured to generate a base frequency clock. The first divider circuit is configured to divide the base frequency clock by a first selectable divisor to generate a divided clock. The synchronization control circuit is configured to generate a synchronization pulse that controls a change of the first selectable divisor in the first divider circuit from a first value to a second value. A pulse width of the synchronization pulse is based on the first value of the first selectable divisor. The peripheral circuit is coupled to the first divider circuit and the synchronization control circuit. The peripheral circuit includes a second divider circuit. The second divider circuit divides the divided clock by a second selectable divisor, and change the second selectable divisor responsive to the synchronization pulse.

Clock synchronization pulse width scaling

In an example, a system includes a phase-locked loop including a charge pump coupled to a phase frequency detector, a low-pass filter coupled to the charge pump, and a VCO coupled to the low-pass filter, where the charge pump is configured to provide a charge pump current to the low-pass filter. The system also includes a current source configured to provide a bias current to the charge pump. The system includes a first bias compensation circuit configured to increase the bias current responsive to a control voltage provided to the VCO being within a first range. The system also includes a second bias compensation circuit configured to decrease the bias current responsive to the control voltage provided to the VCO being within a second range.

Loop bandwidth control for fractional-n frequency synthesizer

A system includes a ring oscillator including an odd number of inverters arranged in a ring. The system also includes a time to digital converter including an odd number of flops, where each of the flops is coupled to an output of a different inverter. The system includes a level shifter coupled to the inverters and to the flops. The system also includes a Gray counter coupled to at least one of the flops. The system includes a decoder coupled to the time to digital converter. The system also includes a phase frequency detector coupled to the decoder.

Metastability correction for ring oscillator with embedded time to digital converter

A glitch filter system includes an input stage to receive an input signal, a first output to provide a first digital signal, and a second output to provide a second digital signal. A C-element of such system receives the first digital signal and the second digital signal and provides a third digital signal at a first logic state in response to each of the first and second digital signals having a second logic state opposite the first logic state. An output latch of such system provides an output signal at the second logic state in response to the first logic state of the third digital. The output latch also receives the first and second digital signals to maintain the first logic state of the third digital signal in response to one of the first and second digital signals changing from the second logic state to the first logic state.

Glitch filter system

One example includes a glitch filter system. The system includes an input stage to receive an input signal, a first output to provide a first digital signal, and a second output to provide a second digital signal. A C-element receives the first digital signal and the second digital signal and provides a third digital signal at a first logic state in response to each of the first and second digital signals having a second logic state opposite the first logic state. An output latch provides an output signal at the second logic state in response to the first logic state of the third digital. The output latch also receives the first and second digital signals to maintain the first logic state of the third digital signal in response to one of the first and second digital signals changing from the second logic state to the first logic state.

Digital control of a crystal oscillator is implemented in a manner that allows frequency accuracy to be traded off dynamically with power consumption. The oscillator transitions between a less accurate/lower power mode and a high accuracy/higher power mode smoothly without requiring any external clock source during the transition. Power consumption is optimized because the crystal oscillator provides the clock source during transitions between the power modes and no other clock source is needed for these transitions. The system can also optimize the startup time and steady state power consumption independently.

Multi-mode crystal oscillators

A circuit includes a crystal oscillator to generate an output frequency for a circuit. A driving oscillator generates a startup signal having a driving frequency that is provided to activate the crystal oscillator. The driving frequency of the startup signal is varied over a range of frequencies that encompass the operating frequency of the crystal oscillator to facilitate startup of the crystal oscillator.

Driving crystal oscillator startup at above, below and operating frequency

In an electronic device, an RC oscillator generally includes a resistor, a capacitor and at least one inverter. The resistor and capacitor generate a time-varying voltage. The time-varying voltage is provided to the at least one inverter to cause a clock signal to propagate therethrough. The clock signal propagates with a time delay that is at least partially dependent on a supply voltage. The supply voltage is adjusted to maintain the time delay at almost a constant value.

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Ryan Alexander Smith