Samsung Electronics Co., Ltd.

Cadence Design Systems, Inc.

Rwik Sengupta

Mark Stephen Rodder

Joon Goo Hong

Titash Rakshit

Borna Josip Obradovic

Ryan M Hatcher

Jorge A Kittl

Dharmendar Reddy Palle

Raheel Azmat

Ganesh Hegde

Kwanyoung Chun

Chulhong Park

Vassilios Gerousis

Kevin Michael Traynor

Harsono S Simka

Wei-E Wang

Jung Ho Do

Chris Bowen

Jonathan R Fales

Joshua David Tygert

Timothy H Pylant

Tanya Abaya

David Seo

Matthew S Berzins

Robert Christopher Bowen

Andrew Paul Hoover

Hyun-jong Lee

Philippe Hurat

Jeffrey E Nelson

Yusun Lee

Sam Tower

Mohammad Ali Pourghaderi

Kota Oikawa

Kim Changhwa

Sooyeon Jeon

Jac Paul P Condella

A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.

Semiconductor cell blocks having non-integer multiple of cell heights

A cell architecture for vertical field-effect transistors (VFETs) is provided. The cell architecture includes: top source/drain (S/D) contact structure having a square shape in a plan view; and horizontal metal patterns formed on the top S/D contact structures and extended in an X-direction to be connected to a vertical pattern through with an output signal of a logic circuit formed by the VFETs. The cell architecture further includes a gate contact structure formed on a gate connection pattern connecting gates of the VFETs, wherein a super via is formed on the gate contact structure to receive an input signal of the logic circuit.

VFET standard cell architecture with improved contact and super via

Various embodiments provide for context-aware circuit design layout construct, which may be part of electronic design automation (EDA). In particular, some embodiments enable use of a circuit design layout construct with a layout of a circuit design (hereafter, a circuit design layout), where a programmable pattern of layout shapes of the circuit design layout construct can be inserted into a circuit design layout and can be adapted based on context information associated with the location of its placement within the circuit design layout.

Context-aware circuit design layout construct

A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs

Disclosed are method(s), system(s), and article(s) of manufacture for implementing an approach to facilitate traceability and tamper detection of electronic designs. This approach allows for tracing and tamper detection at any stage of design and manufacturing, such as during layout generation, post-design, post-mask, and post manufacturing of the electronic designs.

Electronic design tracing and tamper detection using automatically generated layout patterns

Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using a processor, an initial data set associated with an electronic design and performing a built in self-discovery (BISD) analysis based upon, at least in part, the initial data set. Embodiments may include displaying, at a graphical user interface, a plurality of tiered, user-selectable options and receiving a user input corresponding to a selection of at least one of the plurality of tiered, user selectable options. Embodiments may also include tuning the plurality of tiered user selectable options based upon, at least in part, the user input.

System and method for device placement

A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET being connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, a third FET and a third resistive memory element connected to a drain of the third FET, and a fourth FET and a fourth resistive memory element connected to a drain of the fourth FET, the drain of the third FET is connected to a gate of the fourth FET and the drain of the fourth FET being connected to a gate of the third FET.

4T4R ternary weight cell with high on/off ratio background

A weight cell, an electronic device and a device are provided. The weight cell includes a first resistive memory element and a second resistive memory element, a select transistor, and a layer of Spin Hall (SH) material disposed between the first resistive memory element and the second resistive memory element, the layer of the SH material including a first contact and a second contact. The first contact of the SH material is connected to a drain of the select transistor and the second contact of the SH material is connected to an external word line.

System and method for efficient enhancement of an on/off ratio of a bitcell based on 3T2R binary weight cell with spin orbit torque MJTs (SOT-MTJs)

An integrated circuit (IC) apparatus and a method of forming a conductive material in a backside of an IC are provided. The IC apparatus includes a substrate including a frontside and a backside; at least one first insulating material deposited in the backside of the substrate in a form of a trench; a conductive material deposited in each of the at least one first insulating material; at least one second insulating material deposited on the conductive material to insulate the conductive material from the substrate; an epitaxial crystalline material grown on the frontside of the substrate; at least one semiconductor component formed in the epitaxial crystalline material; and at least one via formed in the substrate to connect the conductive material to the at least one semiconductor component.

Apparatus and method of forming backside buried conductor in integrated circuit

A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. A first portion of the circuit elements are connected to a first portion of the connective components and are active. A the second portion of the circuit elements are connected to a second portion of the connective components and are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry is indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.

Method and system for providing a reverse engineering resistant hardware embedded security module

An integrated circuit including a series of field effect transistors. Each field effect transistor includes a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, and a drain contact on the drain region. Upper surfaces of the source and drain contacts are spaced below an upper surface of the gate by a depth.

Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch

A tap cell configured to enable electrical connection from a buried power rail of an integrated circuit to a power distribution network includes. The tap cell includes a buried power rail layer including VDD and VSS power supply lines, insulating layers and metal layers alternately arranged on the buried power rail layer, a first power supply interconnect in metal layer M1 or higher electrically coupled to the VDD power supply line, and a second power supply interconnect in metal layer M1 or higher electrically connected to the VSS power supply line. The first power supply interconnect and the second power supply interconnect are configured to be electrically connected to the power distribution network, and the VDD and VSS power supply lines are configured to supply power from the power distribution network to the buried power rail of the integrated circuit. The tap cell is free of any active semiconductor devices.

Power distribution network using buried power rail

Growing community of inventors

Austin, TX, United States of America

Rwik Sengupta