No. 24 Research Institute of China Electronics Technology Group Corporation

Chongqing Gigachip Technology Co. Ltd.

China Electronic Technology Corporation, 24th Research Institute

China Electronics Technology Group Corporation No. 24 Research Institute

No. 24 Research Institute of China Electronic Technology Corporation

No. 24th Research Institute of China Electronics Technology Group Corp

Ruzhang Li

Guangbing Chen

Dongbing Fu

Yuxin Wang

Gangyi Hu

Jian'an Wang

Ting Li

Daiguo Xu

Yong Zhang

Tao Liu

Yabo Ni

Hequan Jiang

Yan Wang

Zhengbo Huang

Jianan Wang

Lu Liu

Xu Wang

Minming Deng

Liang Li

Zhengping Zhang

Xueliang Xu

Hanfu Shi

Xiaofeng Shen

Mingyuan Xu

Can Zhu

Jie Pu

Zhou Yu

Youhua Wang

Shiliu Xu

Zicheng Xu

Peijian Zhang

Huaiqiang Yu

Chao Chen

Jun Luo

Xingfa Huang

Kaizhou Tan

Yonghui Yang

Shengdong Hu

Zhaohuan Tang

Yi Zhong

Sheng Qiu

Jun Liu

Tian Xiao

Jiahao Zhang

Jun Yuan

Ruitao Zhang

Junan Zhang

Shutao Zhou

Kaiquan He

Xian Chen

Zhengyuan Zhang

Yonghong Dai

Feiyu Jiang

Xiyi Liao

Peng Wang

Xiaojun Fu

Zhihua Feng

A method for correcting an analog-to-digital converter includes the following steps: extracting gain errors and weight errors of all conversion stages of an analog-to-digital converter; performing first correction on the analog-to-digital converter based on the gain errors and the weight errors; extracting jitter errors of all conversion stages of the analog-to-digital converter after the first correction; and performing a second correction on the analog-to-digital converter based on the jitter errors. According to the disclosure, the gain errors, the weight errors, and the jitter errors of all conversion stages are successively extracted, and then the analog-to-digital converter is corrected. Precision after the corrections is higher. An actual weight of each quantization unit at each conversion stage, an actual inter-stage gain of each conversion stage and an actual weight of jitter are extracted, impact of a jitter weight is eliminated during outputting, and a signal-to-noise ratio of analog-to-digital conversion is increased.

Method for correcting analog-to-digital converter

A method for calibrating an analog-to-digital converter includes the following steps: conducting an initial performance test and judgement on the analog-to-digital converter; if the initial performance test succeeds, performing a pre-trimming and judgement on the analog-to-digital converter; if the pre-trimming succeeds, performing an error extraction on the analog-to-digital converter, obtaining errors of conversion stages of the analog-to-digital converter; performing an error soft trimming and test on the analog-to-digital converter according to the errors of the conversion stages; and if the error soft trimming and test of the analog-to-digital converter succeed, performing an error hard trimming and test on the analog-to-digital converter according to the errors of the conversion stages.

Method for calibrating analog-to-digital converter

The disclosure provides a power semiconductor device and manufacturing method thereof. A plurality of second resistive field plate structures extending through an epitaxial layer in a first direction into a substrate are arranged in a termination region of the epitaxial layer and the plurality of second resistive field plate structures are arranged radially in a first plane. A plurality of tightly coupled second resistive field plates extending from a side close to a cell region to a side far away from the cell region form a more uniform three-dimensional electric field distribution diverging around the cell region, which optimizes a guiding and binding effect on a charge in a space depletion region of the cell region and improves a withstand voltage performance of the whole power semiconductor device.

Power semiconductor device and manufacturing method thereof

A differential-follower control circuit has been provided, comprising: a follower; an output-voltage following module, which controls a voltage at a control terminal of the follower to vary with an output voltage; a substrate-voltage following module, which controls a substrate voltage of an output transistor of the follower to vary with an input voltage; an output terminal of the follower is connected to a first terminal of the output-voltage following module; a second terminal of the output-voltage following module is connected to the control terminal of the follower; a first terminal of the substrate-voltage following module is connected to an input terminal of the follower and a second terminal of the substrate-voltage following module is connected to a substrate of the output transistor; the invention effectively improves the overall linearity of the follower.

Differential-follower control circuit

The comparator includes an input unit, a load unit, a control switch, and an adjustment unit. The input ends of the input unit are connected to a first input signal and a second input signal. The load unit is connected to the input unit, and the gain of the comparator is adjusted by changing the gate voltages of the pair of gain adjustment transistors of the load unit. The adjustment unit is connected to the input unit, and the gate voltages of the pair of gain adjustment transistors are adjusted according to the enable state of the control switch. The present disclosure also provides an analog-to-digital converter.

Comparator and analog-to-digital converter

A follow-hold switch circuit comprising: a follower; a sampling sub-circuit for voltage sampling; a bootstrap-control sub-circuit, which provides a bootstrap voltage to the sampling sub-circuit when the circuit is in a following state; a sampling-switch-control sub-circuit, which provides a common-mode voltage to a bootstrap capacitor in the bootstrap-control sub-circuit when the circuit is in a holding state; the follower is connected to an output of the sampling sub-circuit; the sampling sub-circuit is connected to the bootstrap-control sub-circuit and the sampling-switch-control sub-circuit respectively through a sampling switch; the present disclosure can effectively improve the linearity of sampling switches.

Follow-hold switch circuit

An interface circuit and an electronic apparatus, including: a programmable current array (), generating a first current and a second current transmitted to a common mode and differential mode generation circuit () according to an input code, and a third current and a fourth current transmitted to a driving bias generation circuit () according to the input code; the common mode and differential mode generation circuit (), generating a common mode voltage according to the first current, and generating a high level voltage and a low level voltage according to the second current and the common mode voltage; a driving bias generation circuit (), simulating a load according to the third and fourth currents, and generating a bias voltage based on the load and the low and high level voltages; an output driving circuit (), converting an input signal into a differential signal in which the common mode voltage and a differential mode amplitude are configurable.

Interface circuit and electronic apparatus

A voltage control method and a voltage control circuit for an anti-fuse memory array, including: obtaining a storage data address, dividing the storage data address into multiple subdata addresses, decoding each subdata address to obtain a corresponding group of decoder output signals, converting the corresponding group of decoder output signals into a group of control signals by a corresponding group of high voltage converters; connecting multiple groups of data selectors in series, outputting selection voltages input to each group of data selectors to an anti-fuse unit under the control of the corresponding group of control signals; programming or reading an anti-fuse unit; the selection voltages include one of a programming selection voltage, a reading selection voltage, and a non-designated selection voltage. The present disclosure reduces the number of transistors and saves layout areas when the programming or reading operation is performed.

Voltage control method and voltage control circuit for anti-fuse memory array

A pipelined analog-to-digital converter and an output calibration method for the same. The pipelined analog-to-digital converter introduces an error calibration mechanism on the basis of traditional pipelined analog-to-digital converters through a control module, an equivalent gain error extraction module, an error storage module and a coding reconstruction module to compensate for gain errors and setup errors caused by operational amplifiers in a pipelined conversion module, so that the analog-to-digital conversion accuracy is improved, and requirements for the gain and bandwidth of the operational amplifier are relaxed, which can effectively reduce the power consumption of the analog-to-digital converter and the complexity of the corresponding analog circuit; a curve fitting method is adopted to obtain an ideal output sequence and then calculate errors; meanwhile, extraction and calibration of equivalent gain errors are all done in digital ways, and therefore accuracy thereof is high.

Pipelined analog-to-digital converter and output calibration method thereof

SAR ADC and sampling method based on single-channel TIS. The SAR ADC comprises: a capacitor array comprising a weight capacitor and a compensation capacitor, a first switch array, a second switch array, a channel switch group and a sampling switch; when in a sampling state: a lower plate of the weight capacitor is connected to an input voltage by means of the first switch array, and an upper plate of the capacitor array is connected to a common mode voltage by the sampling switch and the channel switch group; when in a successive approximation state: the lower plate of the weight capacitor is connected to a reference voltage by the second switch array. Input signals are sampled by using a unified to sampling switch, which solves the problem in the traditional technology that sampling moments are mismatched due to different sampling signals in each time-interleaved channel.

SAR ADC and sampling method based on single-channel time-interleaved-sampling

The present disclosure provides a buffer circuit and a buffer. The buffer circuit includes: an input follower circuit for following the voltage change of the first input signal; an input follower linearity boosting circuit for improving follower linearity of the input follower circuit; a first voltage bootstrap circuit for bootstrapping the voltage of the first input signal; a second voltage bootstrap circuit for bootstrapping the voltage of the second input signal; a third voltage bootstrap circuit for providing corresponding quiescent operation point voltage; a compensation follower circuit for following the compensation voltage; a compensation follower linearity boosting circuit for improving follower linearity of the compensation follower circuit; a first load for collecting the buffered voltage; a bias circuit for providing a bias current for the buffer; a bias linearity boosting circuit for improving linearity of the bias circuit; a second load for generating a nonlinear compensation current.

Buffer circuit and buffer

The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates. Compared with traditional divide-by-2 frequency division clock circuits based on D-flip-flop, the low-jitter frequency division clock circuit of the present disclosure has fewer logic gates, a shorter delay, and lower jitter.

Low-jitter frequency division clock clock circuit

Provided in the present invention is a transconductance amplifier based on a self-biased cascode structure. The transconductance amplifier includes a self-biased cascode input-stage structure constituted by PMOS (P-channel Metal Oxide Semiconductor) input transistors M, M, Mand M, a self-biased cascode first-stage load structure constituted by NMOS (N-channel Metal Oxide Semiconductor) transistors M, M, Mand M, a second-stage common-source amplifier structure constituted by an NMOS transistor Mand a PMOS transistor M, a bias circuit structure constituted by NMOS transistors Mand Mand a PMOS transistor M, an amplifier compensation capacitor C, an amplifier load capacitor C, a reference current source Iref and a PMOS transistor Mthat provides a constant current source function. Further provided in the present invention is a transconductance amplifier based on a self-biased cascode structure, which adopts an NMOS transistor as an input transistor. Both input transistors and load transistors of a first-stage amplifier of the present invention adopt self-biased cascode structures, such that the output impedance and the DC gain of the first-stage amplifier are increased. Substrate voltages of the MOS transistors of the first-stage amplifier are provided by an amplifier bias circuit. Owing to a connection mode of the compensation capacitor C, a higher figure of merit is achieved.

Transconductance amplifier based on self-biased cascode structure

The present disclosure provides a pipelined analog-to-digital converter having input signal pre-comparison and charge redistribution, including: one-stage or multi-stage of pipelined structure unit, a first flash analog-to-digital converter, and an adjusting output unit. Each stage of the pipelined structure unit is used to quantify the input signal. The first flash analog-to-digital converter quantizes a residual signal output by a final pipelined structure unit, and outputs a corresponding quantized value. The adjusting output unit combines each of the quantized values according to a connection order of the multi-stage pipelined structure unit and a flash analog-to-digital conversion unit to output a complete quantization result. By using the pre-comparison and charge redistribution technologies, the number of comparators of different stages of pipelined sub ADC is reduced and the low power consumption design is achieved, signal sample-and-hold and residual signal amplification establishing are simultaneously carried out, thus improving the conversion rate.

Pipelined analog-to-digital converter having input signal pre-comparison and charge redistribution

The present disclosure provides a high-speed and low-noise dynamic comparator, which includes: an input unit, including an input NMOS transistor and an input PMOS transistor; a latch unit, including a latching NMOS transistor and a latching PMOS transistor, where the latching NMOS transistor and the latching PMOS transistor are connected to form a latch structure; a pull-up unit, including a pull-up PMOS transistor connected to the input NMOS transistor; and a substrate bootstrap voltage generation circuit, generating a substrate bootstrap voltage. In the present disclosure, a substrate bootstrap technology of MOS transistors is used, thereby reducing on resistances of the MOS transistors and improving the comparator speed; threshold voltages of the input transistors of the comparator are reduced, transconductance of the input transistors is increased, thereby reducing equivalent input noise of the comparator, and as a common-mode voltage of the comparator changes, a comparison delay changes relatively little.

High-speed and low-noise dynamic comparator

Growing community of inventors

Chongqing, China

Ruzhang Li