Rambus Inc.

Marvell Asia Pte., Ltd.

Agere Systems Inc.

Marvellworld Trade Ltd.

Ruwan Ratnayake

Brian S Leibowitz

Hae-Chang Lee

Jihong Ren

Erich Franz Haratsch

Mats Oberg

Nedeljko Varnica

Nitin Nangare

Noam Mizrahi

Konstantin Kudryavtsev

Leo Jiang

Igor Polivanyi

Wen Lung Chang

Quynh Chau

An integrated circuit (IC) chip includes transfer circuitry to transfer signals between the IC chip and a second IC chip. The transfer circuitry includes equalization circuitry having at least one tap to equalize the signals. The equalization circuitry includes a tap weight adapter circuit to generate a respective tap weight for each of the at least one tap based on edge information of previously transferred signals.

Edge based partial response equalization

An intergrated circuit (IC) chip includes receiver circuitry to receive signals from a second IC chip. The receiver circuitry includes equalization circuitry having at least one tap to equalize the signals. The equalization circuitry includes a tap weight adapter circuit to generate at least one tap weight corresponding to the at least one tap based on edge information of previously received signals.

This disclosure describes methods and systems for high-throughput computations in a fully-connected deep neural network. Specifically, a hardware-based deep neural network architecture including a set of parallel node processors is used to process node value transition between layers of the deep neural network, which usually involves a large-scale matrix multiplication. The set of parallel node processors are configured to decompose the large-scale matrix multiplication into sub-matrix multiplications with smaller sizes and thus reducing the hardware-complexity and making feasible direct implementation in hardware. With this implementation deep neural network may achieve a very high throughput and can handle a large number of processing layers.

Systems and methods for high-throughput computations in a deep neural network

A storage control device coupled to a storage device and located remotely from a host device receives media object data from the host device. The storage control device identifies a type of the media object data and select, based on the identified type, a computational model from among a plurality of computational models for use by a computational engine of the storage control device. The computational engine uses the selected computational model to generate metadata describing the media object data. The metadata is stored in the storage device so as to be selectively retrievable from the storage device separately from the media object data.

Systems and methods for generating metadata describing unstructured data objects at the storage edge

An integrated circuit (IC) memory device includes receiver circuitry to receive write data from a memory controller. The receiver circuitry includes equalization circuitry having at least one tap to equalize the write data. The equalization circuitry includes a tap weight adapter circuit to adaptively generate a tap weight for the tap from an edge analysis of previously received write data.

An integrated circuit (IC) memory controller includes receiver circuitry to receive read data from a memory. The receiver circuitry includes equalization circuitry having at least one tap to apply data level equalization to the read data, and a tap weight adapter circuit. The tap weight adapter circuit adaptively generates a data level tap weight corresponding to the data level equalization from an edge analysis of previously received read data.

A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted by the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value.

A device implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit that sets the tap weights that are used for adjustment of a received data signal. The tap weight adapter circuit sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.

A device () implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit () that sets the tap weights that are used for adjustment of a received data signal (). The tap weight adapter circuit () sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis () may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit () generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.

Partial response decision-feedback equalization with adaptation based on edge samples

Methods and apparatus are provided for decoding codes that can be described using bipartite graphs having interconnected bit nodes and check nodes. A magnitude of a check-to-bit node message from check node j to bit node i is computed based on a sum of transformed magnitudes of bit-to-check node messages for a plurality of bit nodes connected to the check node j, less a transformed magnitude of the bit-to-check node message for bit node i and check node j. A sign of the check-to-bit node message from check node j to bit node i can also be computed by multiplying a product Sof the sign of bit-to-check node messages among a plurality of bit nodes connected to the check node j by the sign of the bit-to-check node message for bit node i and check node j. A decoder architecture is also disclosed for decoding a code that can be described using a bipartite graph having interconnected bit nodes and check nodes. The disclosed decoder can be concatenated with a soft output detector.

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Cambridge, MA, United States of America

Ruwan Ratnayake