International Business Machines Corporation

Globalfoundries Inc.

Ruth Janine Poole

Thomas M Gooding

Brant L Knudson

Cory Lappi

Andrew Thomas Tauferner

Michael K Gschwind

Valentina Salapura

Dong Chen

Paul William Coteus

Michael A Blocksome

Alan G Gara

Joseph D Ratterman

Philip Heidelberger

Adam James Muff

Todd Edward Takken

Martin Ohmacht

Bruce Martin Fleischer

Alexandre E Eichenberger

Robert William Wisniewski

John A Gunnels

Mark Edwin Giampapa

Burkhard Steinmacher-Burow

Kathryn Mary O'Brien

Mark Gregory Megerian

Sameh W Asaad

Matthias Augustin Blumrich

Shawn Anthony Hall

Thomas Winters Fox

John Kevin O'Brien

Chen-Yong Cher

Barry Marshall Trager

Peng Wu

Charles David Wait

Sameer Kumar

James Anthony Marcella

George L Chiu

Todd Alan Inglett

Krishnan Sugavanam

Gerard Vincent Kopcsay

Jeffrey John Parker

Robert Matthew Senger

Noel A Eisley

David L Satterfield

Douglas R Miller

Craig Brian Stunkel

Rudolf Adriaan Haring

Yutaka Sugawara

Amith R Mamidala

Kristan D Davis

Jose R Brunheroto

Michael B Mundy

Matthew Roger Ellavsky

Robert E Walkup

James Lee Van Oosten

Samuel J Miller

Gabor J Dozsa

Ralph E Bellofatto

Peter Boyle

Norman Christ

Kahn C Evans

William Maupin Stockdell

Alfred Thomas Watson, Iii

Charles J Archer

Brian E Smith

Albert Sidelnik

Larry William Youngren

David Finian Owen

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Multi-petascale highly efficient parallel supercomputer

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

Power throttling may be used to conserve power and reduce heat in a parallel computing environment. Compute nodes in the parallel computing environment may be organized into groups based on, for example, whether they execute tasks of the same job or receive power from the same converter. Once one of compute nodes in the group detects that a parameter (i.e., temperature, current, power consumption, etc.) has exceeded a first threshold, power throttling on all the nodes in the group may be activated. However, before deactivating power throttling, a plurality of parameters associated with the group of compute nodes may be monitored to ensure they are all below a second threshold. If so, the power throttling for all of the compute nodes is deactivated.

Adaptive recovery for parallel reactive power throttling

Embodiments of the invention provide a method for deploying and running an application on a massively parallel computer system, while minimizing the costs associated with latency, bandwidth, and limited memory resources. The executable code of a program may be divided into multiple code fragments and distributed to different compute nodes of a parallel computing system. During program execution, one compute node may fetch code fragments from other compute nodes as necessary.

Distributed schemes for deploying an application in a large parallel system

A method of managing a process relocation operation in a computing system is provided and includes determining respective operating temperatures of first, second and additional nodes of the system, where the first node has an elevated operating temperature and the second node has a normal operating temperature, notifying first and second kernels respectively associated with the first and second nodes, of a swapping condition, initially managing the first and second kernels to swap an application between the first and the second nodes while the swapping condition is in effect, and secondarily managing the first and second kernels to perform a barrier operation to end the swapping condition.

Temperature threshold application signal trigger for real-time relocation of process

Methods, apparatus, and products for distributing parallel algorithms of a parallel application among compute nodes of an operational group in a parallel computer are disclosed that include establishing a hardware profile, the hardware profile describing thermal characteristics of each compute node in the operational group; establishing a hardware independent application profile, the application profile describing thermal characteristics of each parallel algorithm of the parallel application; and mapping, in dependence upon the hardware profile and application profile, each parallel algorithm of the parallel application to a compute node in the operational group.

Mapping and distributing parallel algorithms to compute nodes in a parallel computer based on temperatures of the compute nodes in a hardware profile and a hardware independent application profile describing thermal characteristics of each parallel algorithm

An apparatus, program product and method manage a queue through the use of element-based journaling to record changes made to logical elements in a queue. In contrast to convention memory-based journaling, where any changes to the memory representing an element in a queue are journaled, only those operations that affect the logical ordering and/or placement of an element on a queue, or the logical contents of such an element, are journaled. Memory management operations such as pointer manipulation operations that modify pointers or other memory management data, but do not otherwise modify the actual elements in a queue or their relative ordering, need not be journaled. As a consequence, the storage and processing overhead associated with journaling may be substantially reduced, thereby substantially reducing the overhead associated with maintenance and recovery of a queue.

Automated queue recovery using element- based journaling

Growing community of inventors

Rochester, MN, United States of America

Ruth Janine Poole