Intel Corporation

Apple Inc.

Rustam Miftakhutdinov

Gautham N Chinya

Julien Sebot

Eric Kwesi Donkoh

Rangeen Basu Roy Chowdhury

Stephen J Tarsa

A prefetcher circuit with dynamic, root function-based trigger point selection is disclosed. A processor includes an instruction cache and a call stack having entries that store indications of functions called in an instruction stream. A prefetcher is configured to, in response to detection of an instruction cache miss, determine, based on entries in the call stack, a depth of a deepest function of the sequence of functions that remains in the call stack over an interval preceding the instruction cache miss. The prefetcher is further configured to select a trigger point based on the determined depth, and select a training signature based on the selected trigger point. In response to subsequently detecting the training signature, the prefetcher is configured to generate a prefetch request to prefetch instructions into the instruction cache.

Prefetcher circuit with dynamic trigger point

A system on a chip is described that comprises a processor and a set of memory components that store instructions, which when executed by the processor cause the system on a chip to: generate, by a set of data collectors of a telemetry subsystem, a set of streams of telemetry metadata describing operation of the processor, forward one or more streams of telemetry metadata from the set of streams of telemetry metadata to a set of machine learning-driven adaptation decision models, receive, from the set of machine learning-driven adaptation decision models, a set of configuration parameters for controlling operation of the processor based on the one or more streams of telemetry metadata, and modify operation of the processor based on the set of configuration parameters.

Reducing microprocessor power with minimal performance impact by dynamically adapting runtime operating configurations using machine learning

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Hillsboro, OR, United States of America

Rustam Miftakhutdinov