Intel Corporation

Crosscheck Technology, Inc.

Samsung Semiconductor & Telecommunication Co., Ltd.

Rustam J Mehta

Tushar R Gheewala

Michael Geilhufe

Stephen F Dreyer

Timothy Saxe

Lubin Y Gee

Hyung-Kyu Lim

Pearl Cheng

Yogendra Bobra

Jae-Yeong Do

Prab Varma

A storage element for testing delay paths in integrated circuits is described. The storage element may be used in integrated circuits having matrices of probe and sense lines. The storage element generates a logic transition on an input to a delay path, the logic transition being closely synchronized with a clock signal. The storage element comprises a data input and a data output coupled to the input to the delay path. A master latch receives data from the data input through a first switch, the first switch being controlled by the complement of the clock signal. A slave latch receives data from the master latch through a second switch, the second switch being controlled by the true of the clock signal. A first sense input loads a first logic state into the master latch through a third switch, the first sense input being coupled to one of the IC's sense lines. The third switch is controlled by one of the IC's probe lines. A second sense input loads a second logic state into the slave latch through a fourth switch, the second sense input being coupled to another one of the IC's sense lines. The fourth switch is controlled by a second control signal. The second logic state replaces the first logic state in the slave latch upon application of the clock signal. The desired signal transition is generated where the first logic state is different from the second logic state.

Storage element for delay testing

An integrated circuit structure which employs at least two metal levels overlying an array of circuit elements. Each metal level contains signal routing resources which can be used for supplying power and interconnecting circuit elements. The metal levels include a first metal level directly overlying the array of circuit elements, intermediate metal levels (if there are more than two metal levels), and a top metal level overlying all other metal levels. Power carrying tracks are disposed in the top metal level. Power antennae are disposed in the first metal level, but only where necessary to provide power to the circuit elements. The power antennae are for connecting the power carrying tracks to the circuit elements. Power bridges are disposed in intermediate metal levels between the first metal level and the top metal level. The power bridges are for connecting the power carrying tracks to the power antennae. Contacts to the first metal level are used as a means by which the power antennae are connected to the circuit elements. Vias to the metal levels overlying the first metal level are used as a means by which the power carrying tracks are connected to the power bridges and the power antennae, and by which the power bridges are connected to other power bridges and the power antennae.

Method and structure for routing power for optimum cell utilization with

A normal decoder and a redundant decoder having address program devices are used for the replacement of bad cells. The number of address program devices is one more than the number of input address bits for selecting a normal row or column. The input signals of the additional program device are complementary to the input signals of one of the other program devices. The program of the program devices have two steps to repair the faulty cells. To increase the reliability of redundancy, a nonvolatile memory element used in the program devices is a bridge connected four cell FLOTOX type nonvolatile memory device.

Redundancy circuit for use in a semiconductor memory device

An E.sup.2 PROM is disclosed which provides automatic programming verification. Before data is written into the cells, the cells are automatically erased. The contents of the cells are checked to verify that erasing has been completed. If it has not, erasing is continued until the cells are erased. When data is written into the cells, the writing of the data into the cells continues until programming is verified. The verification is conducted at potentials other than the normal reference potential to assure that the cells are well programmed with either binary zeroes or binary ones.

Intelligent electrically programmable and electrically erasable ROM

A semiconductor memory employs a variety of circuit elements which are used to manipulate the digital information stored within the rows and columns of the memory array. The circuit elements must be manipulated in an ordered sequence with proper relative timing to permit decoding of various addresses and other circuit commands and enabling of various ones of the circuit elements. The plurality of timing signals are generated within the memory by a corresponding plurality of timing generators. Accurate timing and sequencing is obtained by utilizing the output of one timing generator to trigger or initiate the generation of a signal in another generator followed by either proper conditioning upon an input signal, such as an address, or by a predetermined delay designed into the timing generator itself.

Sequential timing circuitry for a semiconductor memory

An improved dynamic MOS RAM employing capacitive storage memory cells having a single active device per cell. The RAM includes several improved circuits and techniques which reduce power consumption and pattern sensitivity and which also provide a higher speed memory. Complementary input/output lines are employed which are coupled to alternate pair of the bit-sense lines making the use of a bistable output latch and push-pull output buffer more advantageous. The sense amplifiers associated with each of the bit lines are activated by a dual sloped signal to reduce noise and increase sensitivity and gain in the amplifiers. The output lines of the address buffers are initially 'high' and then brought to their final level after an address is received by the buffers.

Dynamic MOS RAM

A random access memory system employing dynamic storage wherein each cell comprises a single active element. The memory employs MOS technology and is disposed on a silicon substrate. A plurality of sense amplifiers are disposed in a column substantially bisecting each row of memory cells in the memory array. A single input/output line communicates with all the cells. Two dummy cells are employed on each row line on opposite sides of the sense amplifiers. The value of the signal provided by the dummy cell is approximately mid-way between a '0' signal and a '1' signal provided by the storage cells. A plurality of timing signals are generated within the memory; accurate timing is obtained by utilizing the output of one timing generator to trigger or initiate the generation of a signal in another generator.

Growing community of inventors

Sunnyvale, CA, United States of America

Rustam J Mehta