Bull Hn Information Systems, Inc.

Honeywell Information Systems Inc.

Other

Honeywell Bull, Inc.

Bull Hn

Russell Wayne Guenthner

Clinton B Eckard

William A Shelly

Ronald E Lange

John Edward Heath

Joseph Charles Circello

Leonard Rabins

Albert Henry John Wigchert

F Michel Brown

Charles P Ryan

Leonard G Trubisky

Stefan R Bohult

Bruce E Flocken

Cynthia S Guenthner

Nicholas John Colasacco

David W Selway

Peter C Economopoulos

John E Wilhite

David A Egolf

Ronald W Yoder

David S Edwards

Sidney L Andress

Richard H Ong

Lowell D McCulley

Todd Bradley Kneisel

Donald C Boothroyd

Wayne R Buzby

Bruce A Noyes

Richard L Demers

Gregory C Edgington

Boubaker Shaiek

Jeffrey D Weintraub

R Morse Wade

Ron Yoder

Eric Earl Conway

Rodney B Schultz

William J Brophy

Carlos Macia

Mark T Chase

Sleiman Chamoun

Anthony J Galcik

David Lowell Bowne

Kala J Marietta

Gary R Presley-Nelson

Steven G Mehlberg

Shahrom Kiani

Claude Rabel

Clint B Eckard

Michel F Brown

A scanning camera upgrade adaptor system provides backwards compatibility when an existing scanning camera subsystem is replaced or upgraded in automated sorting equipment with a newer camera having a different data format. The adaptor system allows sorting equipment such as mail sorting equipment to be upgraded or repaired with a new camera while providing compatibility and optional fallback to a previous mode of operation of the existing equipment. The upgrade system enables legacy equipment and newly added sorting/processing equipment to be utilized in conjunction, while reducing cost of upgrade and necessity for completely new equipment as desirable features are added.

Sorting/scanning system camera upgrade apparatus with backwards compatibility

A method is disclosed for determining with computing apparatus an adequate number of clusters for summarizing result data that includes a large number of observation data points. The summary data includes a small number of samples of data from each cluster with the number of clusters being large enough to provide a good summary of all the result data without being so large as to make it difficult for one skilled in the art to examine visually all of the summary data generated by the computing apparatus.

Method for summarized viewing of large numbers of performance metrics while retaining cognizance of potentially significant deviations

A method is disclosed for translating by a computer system of a COBOL computer program into a translated computer program in a readable and maintainable syntax in an object oriented programming language. The translated program including variable names equivalent to the original COBOL variable names and with attributes described in COBOL syntax. The translating method further providing for memory allocation in the translated computer program for storage of 'COBOL' variables compatible with that of the original COBOL program; a description of program flow that is readable, and utilizing arithmetic operators to describe operations between COBOL variables. Also disclosed is a special object oriented run-time library for creating and performing operations between COBOL numeric objects, including maintaining storage of variable content in the original COBOL format, and for enabling readability of the translated source code by allowing arguments for variable type descriptions to be expressed in COBOL syntax.

Method for translating a cobol source program into readable and maintainable program code in an object oriented second programming language

A method, apparatus, and program product are disclosed for carrying out the compilation of an original Cobol program that includes a mix of Cobol, C++ or JAVA and optional OpenMP directives in a single source program file so as to provide improved performance during execution of the program and improved convenience and features in programming. The approach or method includes performing a compilation (or translation) step utilizing a first compiler or translating program which is a is a specialized compiler/translator that takes as input a Cobol source program including a further provision for the inclusion of C/C++ program statements and OpenMP statements, and produces as output an intermediate computer program, the intermediate program that is entirely in C or C++, the intermediate program being intended for further compilation by an existing selected second compiler, the second compiler being an optimizing compiler that provides support for parallelism for the programs described in the C/C++ programming languages.

Method for enabling compilation of a Cobol source program utilizing a two-stage compilation process, the Cobol source program including a mix of Cobol, C++ or JAVA statements, and optional OpenMP directives

A method and apparatus is disclosed for compilation of an original Cobol program with support for improved performance by increased parallelism during execution using multiple threads of processing. The approach includes a two stage compilation process, the first compilation/translation step by a first specialized compiler/translator that takes as input a Cobol source program that includes parallelization directives, and produces as output an intermediate computer program in a second computer programming language, the intermediate program including parallelization directives in the second computer programming language. The intermediate program is then compiled utilizing a selected second compiler that provides support for parallelism described in the second programming language. The approach optionally allows for use of pragmas serving as parallelization directives to the compiler in the original Cobol program or in the intermediate program.

Method and apparatus enabling multi threaded program execution for a Cobol program including OpenMP directives by utilizing a two-stage compilation process

A method and apparatus is disclosed providing an improvement in performance for arithmetic computations by a computer system for calculations which include decimal numeric variables. The improvement in at least one embodiment includes use of a special compiler in cooperation with a special decimal numeric subroutine library. The compiler provides comparative alignment information based upon comparing alignments of a plurality of decimal variables. The decimal subroutine library can then provide improved performance at run time by utilizing the information compared by the compiler at compiler time rather than making those computations repeatedly at run time.

Method and apparatus providing COBOL decimal type arithmetic functions with improved performance

A secure method, apparatus or computer program incorporates a method for entering private information such as a user identifier, password or other secret code comprising at least one symbol or character. According to method in one illustrated embodiment, the user selects characters for input starting from presentation of an initial suggested character, moving under user control to presentation of a user's desired input character, and then followed by the selection by the user of that presented character as a character for data input. The method includes randomizing the timing of the display and/or reaction time to user input so that the number and timing of the key presses required to select any specific desired character for input is made unpredictable. This makes it difficult during entry of information to determine by covert means what specific information is being entered.

Entering an identifier with security improved by time based randomization of input steps

A method and apparatus is disclosed for compilation of an original Cobol program and building an executable program with support for improved performance by increased parallelism during execution using multiple threads of processing. The approach includes a compilation (or translation) step utilizing a first compiler or translating program which is a parallel aware translating first compiler. The parallel aware first compiler is a specialized compiler/translator which takes as input a Cobol source program, and produces as output an intermediate computer program in a second computer programming language, the intermediate program including parallelization directives, the intermediate program intended for further compilation utilizing an existing selected second compiler, the second compiler providing support for parallelism for programs described in the second programming language. The approach optionally allows for use of pragmas serving as parallelization directives to the compiler in the original Cobol program or in the intermediate program.

Method and apparatus for enabling parallel processing during execution of a Cobol source program using two-stage compilation

As manufacturers of very fast and powerful commodity processors continue to improve the capabilities of their products, it has become practical to emulate the proprietary hardware and operating systems of powerful older computers on platforms built using commodity processors such that the manufacturers of the older computers can provide new systems which allow their customers to continue to use their highly-regarded proprietary legacy software on state-of-the-art new computer systems by emulating the older computer in software that runs on the new systems. In an example of the subject invention, a 64-bit Cobol Virtual Machine instruction provides the capability of adding to or improving the performance of legacy 36-bit Cobol code. Legacy Cobol instructions can be selectively diverted, in the host CPU, to a 64 bit Virtual Machine Implementation. The output legacy and new Cobol code is compiled in a dedicated implementation of the Cobol compiler, and the output of the special purpose compiler is emulated in a special purpose software emulator, separate from the main software emulator that handles the normal 36-bit stream of legacy code.

Host computer system emulating target system legacy software and providing for incorporating more powerful application program elements into the flow of the legacy software

Two unique instructions for the instruction set of a target 36-bit machine which is emulated on a host 64-bit machine are provided in order to achieve visibility, to an emulated application program, of a 'containing' word stored in the memory of the host machine. A 'LOAD64' instruction loads the emulator memory location representing an emulated &#x201c;Q&#x201d; (supplementary accumulator) register with the &#x201c;normal&#x201d; 36-bits of the containing word. At the same time, the &#x201c;upper&#x201d; 28 bits of the 64-bit containing word is copied into the emulator memory location representing an emulated &#x201c;A&#x201d; (accumulator) register. Thus, the emulated 36-bit machine &#x201c;sees&#x201d; and can examine the 64-bit word in its entirety. A &#x201c;Store64&#x201d; instruction stores the emulated &#x201c;Q&#x201d; register contents into the lower 36-bits of the 64-bit containing word, and at the same time stores the lower 28 bits of the emulated &#x201c;A&#x201d; register contents into the upper 28 bits of the 64-bit containing word.

Instructions providing new functionality for utilization by a target system program of host system container words during computer system emulation with host word size larger than that of the emulated machine

As fast and powerful commodity processors have been developed, it has become practical to emulate on platforms built using commodity processors the proprietary hardware systems of powerful older computers. High performance is typically a key requirement for a system even when built using emulation software. In a hardware design many special cases and conditions which may cause exceptions are detected by logic operating in parallel with the instruction execution. In software these checks can cost extra cycles of processor time during emulation of each instruction and be a significant detriment to performance. Avoiding some of these checks by relying upon the underlying hardware checks of the host system and then using a signal handler and special software to recover from these signals is a way to improve the performance and simplify the coding of the software emulation system.

Performance improvement for software emulation of central processor unit utilizing signal handler

Instructions to load and store containing words in a computer system emulator with host word size larger than that of emulated machine

This invention relates to the art of computer system emulation and, more particularly, to a computer system emulator in which the functions normally performed by the hardware in a legacy central processor unit are emulated by a software program. The invention is to enhance the emulated instruction set beyond that of the legacy machine such to include as new single instructions a method for invoking operating system functions, with the machine coding of the operating system functions now being performed by machine code native to the new host machine, rather than as a sequence of emulated legacy instructions.

Encapsulation of large native operating system functions as enhancements of the instruction set in an emulated central processor system

A computer system includes a central processing unit, an addressable main memory storing data pages and a page table, and an associative memory. The associative memory stores a plurality of entries in accordance with a low order virtual address component issued by the CPU's processor when access to a given page in main memory is sought. Each entry in the associative memory includes fields respectively holding: 1) a high order virtual address component; 2) a real page address; and 3) a multi-digit validity count. An incrementable multi-digit counter in the CPU stores a current validity count. When access to a data page is sought, a comparator receives: 1) the high order virtual address component of the data page; 2) the high order virtual address component read from the associative memory entry; 3) the multi-digit validity count read from the associative memory entry; and 4) the multi-digit current validity count in the counter. If there is a full match, a switch issues the real page address read from the associative memory entry. If there is not a match, the page table is consulted to obtain the real address of the requested page, and the associative memory is updated accordingly.

Associative memory system with a multi-digit incrementable validity counter

A data processing system contains a processor supporting both Narrow and Wide instructions and Narrow and Wide word size fixed-point and floating-point operands. The processor communicates over a bus utilizing a Wide word size with the remainder of the data processing system consisting of industry standard memory and peripheral devices. Narrow word sized instructions are stored on Wide word-sized storage devices. In a preferred embodiment, the processor bus has a first integer number of significant data lines. The processor is responsively coupled to the processor bus and includes a first decoder for decoding a first set of instructions received over the set of processor data lines, The first set of instructions each contains a second integer number, less than the first integer number, of significant bits. Fixed point arithmetic operations of a first class are performed in response to instruction decode by the first decoder on a first set of fixed point operands received over the set of processor data lines, wherein each of the first set of fixed point operands contains the second integer number of bits. Fixed point arithmetic operations of a second class are performed on a second set of fixed point operands received over the set of processor data lines, wherein each of the second set of fixed point operands contains the first integer number of bits. Corresponding processing is carried out in performing first and second classes of floating point operations.

Processor with different width functional units ignoring extra bits of bus wider than instruction width

Growing community of inventors

Glendale, AZ, United States of America

Russell Wayne Guenthner