Hewlett-packard Company

Russell W Mason

Leon Jacob Sigal

Jeffry D Yetter

Steven T Mangelsdorf

Joel D Lamb

Craig A Heikes

William J Queen

A dynamic logic circuit having additional test circuitry and control, enabling the dynamic logic gate to operate normally during testing or alternatively to force the dynamic logic gate output to a known state during testing to provide a known input for downstream logic. With the additional test circuitry, there is no need for input test signal sequences to propagate logical test vectors to tested nodes. The dynamic logic circuit includes a storage node that is precharged during a precharge cycle and logic circuitry that may discharge the storage node during an evaluation cycle, depending on logic inputs. The logic circuitry discharges through a clock transistor. Additional test circuitry is added to discharge the storage node during the evaluation cycle, in response to a test control signal and a test state signal. When the dynamic logic gate is operating normally during testing, the test circuitry is disabled. When the gate output is to forced into a known state, the clock transistor is disabled, disabling the logic circuitry, and the test circuitry discharges the storage node, depending on the test state signal.

Test-mode control for dynamic logic gates

An address decoder having a predecoder which predecodes n pairs of true/complement address inputs into 2n memory select lines. By predecoding the address inputs in this manner, the number of pull-down FETs in the pull-down string of the NAND decoder may be minimized so as to provide area and speed advantages. Predecode is provided in a preferred embodiment by logically ANDing the respective true/complement addresses in address pairs to provide a unique predecode value to the decoder. In order to minimize the number of input lines, a decoder only receives inputs over the predecode lines having predecoded addresses unique to that decoder.

Domino style address predecoder

A memory device having a plurality of read ports which can be dumped simultaneously without affecting the data stored in the memory cells of the memory device. The read ports of the memory device of the invention include dump circuits comprising a pair of small NFETs which logically AND the values stored in the memory cell with a READ input signal and then pull low a precharged output line only when both of these signals are true. Each such read port dump circuit is electrically isolated from the others so that multiple read ports can be dumped simultaneously with affecting the data stored in the memory device. Also, by placing only a single transistor in the read port discharge path, the dump circuit may be small and have a minimal impact on write setup time in accordance with the invention.

Memory device with multiple read ports

A technique for encoding multiple floating point formats into a double precision floating point number by padding single word floating point numbers with zeros to form a 64-bit double word in a way that allows a single precision arithmetic logic unit to be built on top of a double precision arithmetic logic unit. The formatting circuitry of the invention requires only small differences in the hardware for single and double precision operations so as to simplify the arithmetic logic unit and the multiplier of the floating point processing units. The encoding technique of the invention includes right justifying the exponent and mantissa of the floating point number in a 'common format' such that rounding of the mantissa need only occur in one place, thereby greatly simplifying the rounding procedure. The technique of the invention also removes multiplexers from critical speed paths in the floating point processing units when it is desired to accommodate multiple data formats.

Common format for encoding both single and double precision floating

A floating point processor in which floating point register file write enables are self-timed from the exception flags from the respective floating point processing units. This self-timing is achieved by forming the floating point processing units from self-timed logic gates which gate data in accordance with the values of the data itself. In other words, the output of a logic gate is made valid only when all inputs to the logic gate have been evaluated as being valid. Since the floating point exception signals from the floating point processing units are also self-timed and no longer edge triggered, the results of the floating point operation may be written to the register file on the same phase in which the result and the exception flags become valid, thereby allowing processing latency to be reduced by a state. Hence, if there is a floating point exception during a floating point operation, the register cell is not written. The floating point exception flags are also precharged to a true level and remain true until it is conclusively determined that a floating point exception will not result from the current floating point operation. At that time, the register cell is immediately written.

Qualification of register file write enables using self-timed floating

A clocking methodology for VLSI chips which uses global overlapping clocks plus locally or remotely generated non-overlapping clocks. Two overlapping clocks and two non-overlapping clocks are thus available in each block of a chip for use as timing edges. The global overlapping clocks are used where possible to provide timing advantages, while the non-overlapping clocks are used to eliminate race conditions as data propagates down a pipeline of transparent registers. Generally, one non-overlapping clock has an edge which must fall before a clock edge of the other non-overlapping clock rises and an edge which must rise after a clock edge of the other non-overlapping clock falls. These signals may be applied to adjacent stages to prevent race conditions; however, the 'dead' time between the falling of one clock edge and the rising of the other clock edge has performance costs. Overlapping clocks are used whenever such race conditions can be avoided, as at the ends of the register pipeline, with the resultant performance improvement. The non-overlapping clock signals are preferably derived from the overlapping clock signals inside each block rather than globally so that it is easier to control the skew between phases of the non-overlapping clock signals. Such use of local non-overlapping clock generators in each block also reduces the amount of capacitive loading on the global overlapping clock network, thereby allowing faster edges and smaller skews on the global overlapping clock which further improves the performance of critical timing paths which use the global overlapping clock.

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Ft. Collins, CO, United States of America

Russell W Mason