International Business Machines Corporation

Russell W Lavallee

William Wu Shen

Kevin W Kark

Philip M Ryan

Vincent F Sollitto, Jr

Walter Heinrich Lipponer

George C Wellwood

Udo Wille

Hartmut Ulland

Kenneth Y Chan

Giacomo Vincent Ingenio

Donald G O'Brien

Charles D Holtz

Michael Rubino

In a computer RAM memory system, the memory is subjected to a self test operation during which data is written to and read out from each address location of the memory. The data read out is compared with the written data to detect errors and the number of errors at each bit position is counted. When the number of errors in a bit position-exceeds a selected threshold, the corresponding DRAM is replaced by a spare DRAM. When the self test detects two or more errors in the same double word, the DRAM corresponding to the bit position having the highest error count is replaced with a spare DRAM. The memory is periodically scrubbed and errors detected during the scrubbing operation are counted for each bit position. At the end of the scrubbing of a chip row the DRAMs corresponding to bit positions at which the error counts exceed a selected threshold are replaced with spare DRAMs. When a multiple bit error in a double word is detected during scrubbing, the corresponding double word is tagged.

Computer RAM memory system with enhanced scrubbing and sparing

A memory interface between the storage controller and memory card of an S/390 system uses the S/390 Storage Protect (SP) Key as an indication or protocol of storage command acceptance by the memory card. When the SP key is returned, then the command is deemed to be accepted by the memory card and the key will be used by the processor for its storage validation in accordance with the S/390 architecture. In the event that the memory card detected an error associated with the command, it will then return an error response code via a memory status bus. The memory status bus is multiplexed to service the existing architected requirement as well as an indicator of handshaking between the memory controller and the memory card.

Memory card interface method using multiplexed storage protect key to indicate command acceptance

A memory control device, having a common synchronous interface coupled thereto, for accessing asynchronous memory devices, as well as other synchronous devices. The memory control device receives, via the synchronous interface, a command having a synchronous format, and translates at least a portion of the command from the synchronous format to an asynchronous format. The command in the asynchronous format is then used to access an asynchronous memory device. The asynchronous memory device can have one of various formats, each of which is supported by the memory control device. The memory control device emulates synchronous memory devices for the system memory controller coupled to the memory control device, even when asynchronous devices are accessed. The memory control device can also translate commands from one synchronous format to another synchronous format such that memory devices of the another synchronous format can be accessed.

Memory control device, with a common synchronous interface coupled

A computer memory maintainence apparatus tests operating system storage and identifies a malfunctioning memory chip in an on-line memory array by detecting and recording all permanent data errors using data comparison along with data complementation and substitutes a spare memory chip for the malfunctioning one for all memory read commands. All write commands are performed on both spare memory and the malfunctioning memory chip. All contents of defective chip are copied to the spare chip. The computer system maintains the scrubbing and a recording counter for each of the data bits in an ECC memory data word. The sparing logic in the memory storage system maintains the bit steering logic and controls for the spare chip. When a counter is incremented above a threshold sparing is invoked to replace the failing bit position. The system writes to the defective and spare chips in parallel even after bit steering is invoked.

Method and apparatus for substituting spare memory chip for

A hierarchical memory system is disclosed comprising at least one dual-ported memory level, each port having access to a separate bidirectional data bus. The port facing the higher memory levels is equipped with a pair of data buffers having a bit width equal to the bit width of a single row of cells in the storage array contained within the dual-ported level. One buffer (output) is loaded in one cycle from the array. The outer buffer (input) is emptied in one cycle into the array. Both buffers interact with the higher memory level independently of the transferring of data through the other of the dual ports. Thus, contention for the use of bus facilities and contention for memory cycles are greatly reduced in the transferring of data between the memory levels.

Hierarchical memories having two ports at each subordinate memory level

A single error correcting memory is constructed from partially good components on the design assumption that the components are all-good. Those small number of logical lines containing double-bit errors are replaced when detected with good lines selected from a replacement area of the memory. The replacement area is provided by a flexibly dynamically deallocated portion of the main memory so that it can be selected from any section of the original memory by inserting the appropriate page address in the replacement-page register. With such a memory architecture until the first double-bit error is detected (either in testing or actual use) all pages may be used for normal data storage. When such an error is detected some temporarily unused page in the memory is deal-located, that is rendered unavailable for normal storage, and dedicated to providing substitute lines. The same procedure is followed for subsequent faults. If the replacement area itself becomes defective, a different page may be chosen to provide substitute lines simply by providing a different address in the replacement page register.

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Lagrangeville, NY, United States of America

Russell W Lavallee