Intel Corporation

Russell W Dyer

Altug Koker

Serafin E Garcia

Abdul H Pasha

David J Harriman

Josh B Mastronarde

Aditya Sreenivas

Himanshu Sinha

The present invention is a method and apparatus to reduce latency in accessing a memory from a bus. The apparatus comprises a pre-fetcher and a cache controller. The pre-fetcher pre-fetches a plurality of data from the memory to a cache queue in response to a request. The cache controller is coupled to the cache queue and the pre-fetcher to deliver the pre-fetched data from the cache queue to the bus in a pipeline chain independently of the memory.

Reducing memory access latencies from a bus using pre-fetching and caching

A method includes reordering a non-linear burst transaction initiated by a processor targeting a peripheral bus to a linear order, and retrieving the linear burst from the peripheral bus.

Reordering of burst data transfers across a host bridge

A device to change the ordering of datums in a packet from a storage device to a pre-determined ordering according to their addresses. The device has a first circuit to receive and process address information to determine a data ordering of data associated with the address information; and a second circuit to reorder the data into ordered packets in the predetermined ordering. This device can be used to efficiently transfer graphic data through the AGP bus in a computer.

Data reordering mechanism for data transfer in computer systems

Dynamic arbitration based on a high priority transaction type. A first memory access request is received at a first request queue. If the first memory access request is of a first type, the priority of the first request queue is dynamically raised over the priority of a second request queue. The priority of the second request queue is dynamically raised over that of the first request queue when requests of the first type in the first request queue, up to a maximum predetermined number of requests, have been serviced.

Method and apparatus for dynamic arbitration between a first queue and a second queue based on a high priority transaction type

An embodiment of a memory controller that improves main memory bandwidth utilization during graphics translational lookaside buffer fetch cycles is disclosed. The memory controller includes a first request path and a second request path. The memory controller further includes a graphics translational lookaside buffer that includes a cache. The graphics translational lookaside buffer issues an address fetch request to a memory interface when a graphics memory request received from the first request path or from the second request path misses the cache. The memory controller also includes a memory arbiter that includes a first request path cycle tracker and a second request path cycle tracker. The memory arbiter allows a request received from the second request path to be issued to the memory interface when a graphics memory request received from the first request path is stalled due to a graphics translational lookaside buffer cache miss.

Method and apparatus for improving system memory bandwidth utilization during graphics translational lookaside buffer cache miss fetch cycles

Method and apparatus for reordering data in X86 ordering

An embodiment of a memory controller that improves processor to graphics device throughput by reducing the frequency of retries of postable write transaction requests is disclosed. The memory controller includes a posted write buffer and a timeout counter. The memory controller is coupled to a processor via a host bus and is also coupled to a graphics device via a graphics bus. If the posted write buffer is unavailable when a first postable write transaction request is received by the memory controller, the memory controller stalls the host bus and waits for the posted write buffer to become available. If a second transaction request is received while the posted write buffers are unavailable, the timeout counter is initiated. If the posted write buffer becomes available before the timeout counter expires, the first postable write transaction request is completed. If, however, the timeout counter expires before the posted write buffer becomes available, the memory controller issues a retry response to the processor, indicating to the processor that the first postable write transaction request must be reissued at a later time.

Method and apparatus for improving processor to graphics device throughput

A data storage array is provided having a number, n, of sequential data storage areas for the storage of data. A valid status array including n bits is provided where there is a one to one correspondence between the bits of the valid status array and the data storage areas of the data storage array. When valid data are written into a data storage area, the status bit of the valid status array corresponding to this data storage area is set to indicate that valid data are present. When data are read out of the data storage area, the corresponding status bit is cleared indicating the absence of valid data. If the data storage array is one that is written to in a random access manner and read from sequentially, as a queue, then the valid status array would indicate the presence of valid data at the head of the queue for the data storage array.

Growing community of inventors

El Dorado Hills, CA, United States of America

Russell W Dyer