Maxtor Corporation

Quantum Corporation

Digital Equipment Corporation

The Quaker Oats Company

Siltronics Ltd.

Digital Equipment Corporation of Canada, Ltd.

Russell W Brown

Mehran Aliahmad

Ivan Chan

Kristopher Kshonze

Bruce A Leshay

Bruce Douglas Buch

Michael D Leis

Bernardo Rub

James David Sawin

Andrew Bishop

Nick Horgan

Michael O Hirtle

Elmer C Simmons

Edward Lloyd Henderson

Arthur D Moore

Michael J Muchnik

Ivan T Chan

Roger H Stowell

Toai A Doan

John A Scaramuzzo

The high frequency components of a SCSI signal are adaptively equalized using an adaptive filter having an adjustable gain. A comparator is used to compare an input signal with a predetermined threshold level. Based on the result of the comparison, the adjustable gain of the adaptive filter is modified.

Mixed signal adaptive boost equalization apparatus and method

A method and apparatus for correcting the timing skew of data signals in a parallel data transmission system, such as Small Computer System Interface (SCSI) data bus, relative to a receive clock in the data bus. The system separately corrects the receive clock duty cycle, and also features independent de-skewing of the rising and falling edges of a data waveform to improve timing accuracy of transmitted signals. The method and apparatus can be used without substantial changes to existing transmission system protocols, and can be implemented on an all-digital integrated circuit.

Timing skew compensation technique for parallel data channels

A circuit for measuring and compensating for DC offset introduced into a differential signal due to, for example, terminator mismatches and interconnect resistance, is described herein. The circuit includes a plurality of capacitors that store test values of a differential signal, a summer, a comparator, a digital counter, and an analog-to-digital converter. The summer sums signals from the plurality of capacitors and a dc offset correction signal from the analog-to-digital converter. A differential output from the summer is processed by the comparator to generate a binary output signal that is used to recursively modify the value of the dc offset correction signal until the dc offset correction signal stabilizes.

Sampled analog DC offset correction for data bus structures

An apparatus mitigates inter-symbol interference effects on an oscillating signal from which digital data will be obtained at a receive end of a channel. The inter-symbol interference is introduced into the oscillating signal as a result of transmitting the oscillating signal through the transmission channel over a substantial distance from a transmit device to the receive end of the channel. A filter element receives an input signal from the transmit device and outputs a filtered signal within a predetermined frequency band. The filter element has a mechanism for adjusting a gain for a given range of frequencies within the predetermined frequency band. The given range of frequencies corresponds to higher frequencies in the predetermined frequency band. An amplitude determining mechanism determines a peak amplitude of the filtered signal. A boost gain control mechanism controls adjustments to the high frequency gain so that the peak-to-peak amplitude of the filtered signal is maintained within a predetermined amplitude range.

Adaptive inter-symbol interference boost equalization apparatus and method

DC offset introduced into a differential signal is compensated for by DC offset correction circuitry. The DC offset correction circuitry receives a known training pattern of alternating logic high and logic low levels (i.e., 10101010 etc.). In one embodiment, the received signal is integrated and the result compared to a predetermined reference level. The result of the comparison is used to adjust a DC offset correction value that is added to the received signal. This process is iteratively performed until successive results of the comparison indicate that the DC offset has been compensated for in another embodiment, the duty-cycle of the received signal is calculated. The result of the duty-cycle calculation is used to iteratively adjust the DC offset correction value.

Apparatus and method for the correction of DC offset in data bus structures at the receiver

An embodiment of the invention provides a method for performing timing de-skew in order to properly receive digital computer information. A sequence of N clock pulses are generated at intervals having phases offset from one another by T/N, where N is at least 2, T is a duration of one bit-cell time, and one cycle of each of the clock phases has a duration of 2T. A test signal is generated at a transmitting portion. The test signal is received, and one of the generated sequences of clock pulses which is aligned with the test signal is identified. The identified one of the generated sequences of clock pulses is used to determine which one of the generated sequences of clock pulses and which polarity to use to receive data.

Method and apparatus for performing clock timing de-skew

A phase difference to duty-cycle circuit converts a phase shifted signal and a reference signal into a single signal having a duty cycle that is a function of the phase difference between the two signals. The single signal may be further converted to a single direct current (DC) value before being transmitted to external measurement circuitry. The external measurement circuitry, by simply measuring the magnitude of the DC signal, can determine the phase difference between the phase shifted signal and the reference signal. In an alternate embodiment, the phase shift in the target bit of a bit pattern is determined based on measurements of the DC voltage value of the shifted target bit pattern, the DC voltage value of first bit pattern comprising a non-shifted bit pattern representing a zero phase shift of the target bit, and a DC voltage value of a bit pattern comprising a non-shifted bit pattern representing a 100% phase shift of the target bit.

High-resolution measurement of phase shifts in high frequency phase modulators

DC offset introduced into a differential signal is compensated for by DC offset correction circuitry. The DC offset correction circuitry receives a known training pattern of alternating logic high and logic low levels (i.e., 10101010 etc.). In one embodiment, the received signal is integrated and the result compared to a predetermined reference level. The result of the comparison is used to adjust a DC offset correction value that is added to the received signal. This process is iteratively performed until successive results of the comparison indicate that the DC offset has been compensated for. In another embodiment, the duty-cycle of the received signal is calculated. The result of the duty-cycle calculation is used to iteratively adjust the DC offset correction value.

Correction of DC offset in data bus structures at the receiver

Momentary contact with a defect site of a data storage disk or free particle by a magnetoresistive read element of a flying head causes momentary heating and unwanted increase in element resistance (thermal asperity) which can disrupt hard disk drive data reading operations. Since the disk carries a predetermined data format, the disk drive controller correlates location of a thermal asperity to the format and thereupon selects from several available thermal asperity recovery methods a method most likely to minimize thermal asperity effect upon disk drive operation during rereading of data at the thermal asperity location.

Method for recovering data from disk with magneto-resistive head in

A phase locked loop has an average zero phase start circuit to detect and correct for the average phase difference between a data signal and a VCO clock signal over a short interval at the beginning of phase-lock acquisition. The average zero phase start circuit has a data comparator to split the data stream into odd and even portions; odd and even pulse position detectors to detect the phase difference between pulses of the odd and even data signals and corresponding pulses of the VCO clock; and a ramp generator to generate a voltage corresponding to the sum of the detected phase differences. The ramp generator employs a capacitor and switched current sources that discharge the capacitor at a fixed rate to generate the voltage. After 4 phase difference measurements are taken, the VCO is stopped, and another current source discharges the capacitor at 4 times the fixed rate. A ramp comparator indicates when the capacitor voltage converges with a reference voltage to restart the VCO in the desired phase alignment with the data signal.

Averaging zero phase start for phase locked loops

Separate charge pumps (58, 60 and 74, 76) drive integral and proportional control paths for a voltage-controlled oscillator (52) in a phase-locked loop (50). A control circuit (74) varies the loop gain of the phase-locked loop by varying the current supplied by the integral-path charge pump (58,60) through a range that is the square of the range through which the current supplied by the proportional-path charge pump (74, 76) is varied. As a consequence, the damping factor of the loop response changes very little as the loop gain is varied through a large range.

Dual-charge-pump bandwidth-switched phase-locked loop

Circuitry and method for generating electrical currents representative of an exponential function of an input current. The circuit includes an input diode chain and an output diode chain. Each of the diodes in the input diode chain has an input current passing therethrough. The input current is produced by an input current source connected in sources with the diode below the cathode of the diode. A voltage driving circuit drives a voltage drop across the output diode chain that has a predetermined relationship to the voltage drop across the input diode chain. The voltage drop across the output diode chain results in a current through the output diode chain. The number of diodes in the output diode chain is preselected relative to the number of diodes in the input diode chain such that the current through the output diode chain is representative of an exponential function of the input current or currents.

Exponential function circuitry

A data decoding circuit which receives an input signal comprising a sequence of pulses and generates a digital data output signal and timing signals in response thereto. The circuit includes a phase-locked loop which generates timing signals in response to the input signal and an offset signal from a data separator circuit. The data separator circuit generates the digital data output signal and the offset signal, which measures the degree of correlation between the input signal as received by the data separator and the timing signal from the phase-locked loop, thereby obviating the need to match the data separator circuit closely to the phase-locked loop.

Data decoding circuit including phase-locked loop timing

Apparatus and method for driving a non-centertapped load such as a loudspeaker from a low voltage supply such as a single dry cell, with increased efficiency. A push-pull signal having similar polarity voltage excursions is applied to opposite terminals of the load. Alternate individual terminals of the load which are opposite to the terminals to which the non-idle phases of the push-pull signal are alternately applied are connected to a common terminal via a pair of transistors. The pair of transistors are driven by an amplified representation of the push-pull input signal. Since pulse signals are not used to drive the pair of transistors, capacitors need not be used to eliminate switching transients which would otherwise appear, and increased efficiency results.

Growing community of inventors

Nepean, Canada

Russell W Brown