International Business Machines Corporation

Russell S Cook

James A O'Connor

Nelson S Xu

Harold J Broker

Joe Christopher St Clair

A method and apparatus for detecting bits set in a data structure. A first level encoding stage receives bits for the data structure, groups the bits into a set of bit groups, and encodes the set of bit groups to form a set of output bits. A set of intermediate level encoding stages is connected to the first level encoding stage. Each level intermediate encoding stage receives output bits from a previous stage, groups the output bits into a plurality of bit groups, and encodes the plurality of bit groups to generate a plurality of output bits. A final level encoding stage is connected to a last intermediate level encoding stage within the set of intermediate level encoding stages, wherein the final level encoding receives final output bits from a last intermediate level encoding stage within the plurality of intermediate level encoding stages and encodes the final output bits to generate an indication of bits set in the data structure.

Apparatus to detect setting of bits in a data structure

A method and apparatus in a geometry engine having a plurality of stages for processing graphics data. An immediate mode data stream is received at a first stage within the plurality of stages. Data from the immediate mode data stream is stored in a storage to build a vertex data structure for processing within the plurality of stages. The vertex data structure is transmitted to the first stage for processing in response to receiving a signal to transmit the vertex data structure. Data for the vertex data structure remains in the storage as default data for a subsequent vertex data structure.

Method and apparatus to handle immediate mode data streams in a data processing system

A high speed digital multiplier utilizes a variation in known shift-and-add algorithms. Each cycle, a single digit of the multiplier and the entire multiplicand are processed to form a 'partial product' that is added to the result of the next cycle. The end result is a two part product, the high order product being generated by a carry-propagate adder, and the low order product being generated by a 'spill adder' that produces one digit each cycle. Inputs of a carry-propagate adder are fed directly from outputs of a carry-save adder rather than running sum and carry registers. With a multiplier digit of 16-bits, a fixed point halfword multiply requires one execution cycle, a fixed point fullword multiply requires two execution cycles, and a floating point long multiply requires four execution cycles with additional overhead if pre- or post-normalization is required.

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Round Rock, TX, United States of America

Russell S Cook