Multiphy Ltd.

Cisco Technology, Inc.

Pmc-sierra Us, Inc.

Maxlinear Asia Singapore Pte Ltd

Russell Romano

Anthony Eugene Zortea

Mark Andrew Webster

Kalpendu Shastri

A method for performing background calibration of interleave timing errors in N order Time-Interleaved Analog to Digital Converters (TIADCs), according to which N samples of the input signal are acquired in N different phases and the time-interleave error of each phase is calculated. Then the sign of each of the time-interleave error is extracted and the errors are adjusted by adjusting the timing of erroneous phases. This process is repeated until all the errors are lower than a predefined level.

Background calibration of interleave timing errors in time-interleaved analog to digital converters

The peak level of a high frequency analog signal in an RF receiver is detected by a system which samples the signal and compares it against a static threshold, generating an above/below status. The system is implemented with a sampler of sufficient aperture bandwidth to capture the signal in question, operated at a clock frequency, dynamically chosen as a function of f(local oscillator frequency) and the desired f(intermediate frequency), to minimize in-band intermodulation products. The sampler produces kickback intermodulation products that are positioned out-of-band, or are of low enough power in-band so as to be inconsequential. Samples are taken for a statistically significant period of time, and the status is used to adapt the threshold to systematically determine the peak amplitude of the signal being observed.

Sampling threshold detector for direct monitoring of RF signals

A method for background calibration of sampler offsets in an Analog to Digital Converter (ADC), according to which one of the samplers of the ADC is established as a reference sampler, whose threshold and timing offsets will be the criterion for adjusting threshold offsets and timing offsets of all other samplers. Then each of the other samplers of the ADC, one at a time, is calibrated by selecting an uncalibrated sampler and establishing it as the current Sampler Under Calibration (SUC); disregarding contribution of the SUC to the output of the ADC; adjusting the threshold of the SUC to be identical to the threshold of the reference sampler; performing one-bit cross-correlation between the reference sampler and the SUC; establishing an error surface representing the threshold offset and timing offset of the SUC with respect to the reference sampler; adjusting the threshold and the timing of the SUC to be equal to the threshold and timing of the reference sampler; restoring level of the SUC to its original threshold with respect to the overall ADC and restoring contribution of the SUC to the output of the ADC.

Background calibration of sampler timing errors in flash analog to digital converters

System and method for the calibration of interleave time errors in an n-level PAM Digital to Analog Converter (DAC), according to which a set of two samplers with adjustable sample time and threshold are introduced at the output of the DAC, which are separated in time. The set of samplers is swept through a n unit interval (UI) window and the n-UI window is classified to periods of transitions and non-transitions on an eye diagram. The relative timing of the lower rate clocks into an n:1 multiplexer is controlled using a control loop, to force equal eye width within the n-UI window and the interleaved timing errors are measured and corrected, until the uneven distribution is being reduced below a predetermined level.

Background calibration of interleaved timing errors in digital to analog converters

Background calibration of sampler offsets in analog to digital converters

A silicon-based optical modulator exhibiting improved modulation efficiency and control of 'chirp' (i.e., time-varying optical phase) is provided by separately biasing a selected, first region of the modulating device (e.g., the polysilicon region, defined as the common node). In particular, the common node is biased to shift the voltage swing of the silicon-based optical modulator into its accumulation region, which exhibits a larger change in phase as a function of applied voltage (larger OMA) and improved extinction ratio. The response in the accumulation region is also relatively linear, allowing for the chirp to be more easily controlled. The electrical modulation input signal (and its inverse) are applied as separate inputs to the second region (e.g., the SOI region) of each arm of the modulator.

Growing community of inventors

Allentown, PA, United States of America

Russell Romano