Nvidia Corporation

Raytheon Company

Oak Technology, Inc.

Russell R Newcomb

Barry A Wagner

William B Simms

Hans Wolfgang Schulze

Shu-Yi Yu

Sunil Rao Sudhakaran

Ashfaq Shaikh

Eric Lyell Hill

Andrew R Bell

Thomas Edward Dewey

Ting-Sheng Ku

James A Wurzbach

Ting Ku

Timothy Hu

David F Ciambrone

Lawrence A Schatzmann

One embodiment of the present invention sets forth a technique for performing high-performance clock training. One clock training sweep operation is performed to determine phase relationships for two write clocks with respect to a command clock. The phase relationships are generated to satisfy timing requirements for two different client devices, such as GDDR5 DRAM components. A second clock training sweep operation is performed to better align local clocks operating on the client devices. A voting tally is maintained during the second clock training sweep to record phase agreement at each step in the clock training sweep. The voting tally then determines whether one of the local clocks should be inverted to better align the two local clocks.

Hardware WCK2CK training engine using meta-EDC sweeping and adjustably accurate voting algorithm for clock phase detection

An interface for implementing a loopback configuration which offers improved calibration and/or testing of an electronic system is disclosed. More specifically, embodiments provide a bi-directional interface with at least two portions or partitions capable of communicating data in opposite directions and implementing a loopback configuration between components of an electronic system, thereby enabling more flexible, efficient and effective calibration and/or testing of the electronic system using a single interface. The loopback of the partitioned bi-directional interface may be used to perform data link training and/or electronic system testing. In one embodiment, the loopback configuration of the interface may be reversible. Additionally, the looped or coupled end of the partitions may be switched from one component to another, thereby reversing the configuration of the loopback in one embodiment. As such, embodiments enable different and/or additional calibration operations and/or tests to be performed when compared with conventional loopback configurations.

Loopback configuration for bi-directional interfaces

Systems and methods for encoding a data word using an 8b/9b encoding scheme that eliminates two-aggressor crosstalk are disclosed. The 8b/9b encoding scheme enables a data word that can be subdivided into portions of eight bits or less to be encoded using code words having one extra bit than the corresponding portion of the data word. Each of the valid code words does not include any three consecutive bits having a logic level of logic-high (i.e., '1'), and represent transition vectors for consecutive symbols transmitted over the high speed parallel bus. An encoder and corresponding decoder are disclosed for implementing the 8b/9b encoding scheme. In one embodiment, the encoder/decoder implements a modified Fibonacci sequence algorithm. In another embodiment, the encoder/decoder implements a look-up table. In some embodiments, data words may be less than eight bits wide.

8b/9b decoding for reducing crosstalk on a high speed parallel bus

Systems and methods for encoding/decoding a data word using an 8b/9b encoding scheme that eliminates two-aggressor crosstalk are disclosed. The 8b/9b encoding scheme enables a data word to be encoded using code words. Each of the valid code words does not include any three consecutive bits having a logic level of logic-high (i.e., '1'), and represent transition vectors for consecutive symbols transmitted over the high speed parallel bus. An encoder and corresponding decoder are disclosed for implementing the 8b/9b encoding scheme. In one embodiment, the encoder/decoder implements a modified Fibonacci sequence algorithm. In another embodiment, the encoder/decoder implements a look-up table.

8b/9b encoding for reducing crosstalk on a high speed parallel bus

A method of receiving data. A plurality of data signals and clocking signals are received over a source synchronous communication channel. The plurality of data signals is strobed with the clocking signal at a plurality of coarse time offset delays (e.g., time offset delays spanning over a data bit period). The plurality of error rates associated with the strobing at the plurality of coarse time offset delays is determined. Strobing design of a transmitting component (e.g., edge-strobed, center-strobed, etc.) may be determined based on the plurality of error rates. The error rates of the plurality of data signals strobed with a plurality of time offset delays close to the determined strobing design of the transmitting component is calculated. A time offset delay is selected based on the error rates. The plurality of data signals can be strobed with the selected time offset delay to recover the transmitted data signals.

Method and system for a free running strobe tolerant interface

A synchronous memory device is configured to switch into and out of a full speed mode to change speed the speed of data transactions without significantly disturbing the frequency of a clock input to a PLL or DLL that provides the internal clock for the synchronous memory device. Since the PLL or DLL receives a clock signal whether or not the synchronous memory device is in a non-full speed mode, the PLL or DLL does not need to settle or relock when the clock signal is reapplied to exit a different speed mode and return to the full speed mode. Therefore, the latency incurred to switch into and out of different speed modes is reduced by eliminating or substantially reducing the time for settling or relocking the PLL or DLL.

Low latency synchronous memory performance switching

Low latency synchronous memory performance switching with drift refresh

Low latency synchronous memory performance switching using update control

Embodiments of power management modes for memory devices are disclosed.

Power management modes for memory devices

Embodiments for positioning transitions in one or more data signals in relation to a data strobe signal are disclosed. For an example embodiment, a receiving device may return a test value to a transmitting device. Timing for one or more data signals may be adjusted in relation to a clock signal according, at least in part, to the test value returned from a receiving device.

Data interface calibration

Embodiments for binary encoding and/or decoding data are disclosed. In one or more embodiments, N data bits may be encoded using one of a plurality of codes derived from at least N+1 bits wherein said one of the plurality of codes is selected to most closely maintain a programmable non-equal ratio of bits at a first logical level to bits at a second logical level.

Binary data encoding/decoding such as for communicating between computing platform components over a parallel interconnect

Embodiments for binary encoding and/or decoding of data for transmission and/or reception over a data interconnect are disclosed. For an embodiment, a code may comprise a base portion, a subset of the base portion, a complement bit associated with the base portion, and a complement bit associated with the subset of the base portion.

Binary data encoding/decoding for parallel bus

Embodiments for binary encoding and/or decoding data are disclosed. In or more embodiments, N data bits may be encoded using one of a plurality of codes derived from at least N+1 bits wherein each of the plurality of codes comprises approximately equal numbers of bits at a first logical level and a second logical level.

Binary data encoding/decoding with error detection, such as for communicating between computing platform components

In a video system in which a video signal source transmits a video signal to a receiver over a transmission line, a method of maintaining a desired voltage level from the video signal source includes the steps of monitoring the level of voltage at the output of the video signal source, and adjusting an input to the video signal source as necessary in order to maintain a desired level of voltage. Thus, when the impedance of the transmission line and receiver change, the output voltage from the video signal source is maintained at a desired level without clipping of the signal when the video signal source is overdriven.

Growing community of inventors

Morgan Hill, CA, United States of America

Russell R Newcomb