International Business Machines Corporation

Russell P Hayes

John D Davis

Paul Alan Bunce

Brian James Yavoich

Embodiments of the present invention are directed to methods, systems, and circuitry for reduced error in power consumption estimation for distinct circuitries. A non-limiting example includes distinct circuitry having an optimized power consumption definition. The distinct circuitry includes a substrate. The distinct circuitry includes an arrangement of interoperable hardware components disposed on the substrate having input pins defined according to a model described by a hardware description language operable to emulate toggle events of the interoperable hardware components defined by the model having a toggle event count based on combinations of the toggle events that correspond to predetermined power quantities. The toggle events define an aggregate toggle power consumption closer to an actual power consumption than an aggregate pin power consumption based on the input pins.

Memory array having power consumption characteristics

A method for testing a circuit includes receiving, by a noise injection circuit, an input signal and generating a noise pulse. Generating the noise pulse includes computing an input resistor pulse, and computing an output resistor pulse. Generating the noise pulse further includes short-circuiting an output resistor substantially simultaneously with opening an input resistor. The method for testing the circuit includes modifying, by the noise injection circuit, the input signal using the noise pulse.

Noise injection circuit

An aspect a bit selection path configured to propagate a bit selection signal. The bit selection path includes bit selection delay circuitry defining a bit selection delay. The memory array includes a row selection path configured to propagate a row selection signal. The row selection path includes row selection delay circuitry defining a row selection delay. The memory array includes local selection circuitry. The local selection circuitry is configured to receive the bit selection signal from the bit selection path before the row selection signal from the row selection path according to the bit selection delay and the row selection delay.

Random-access memory array memory cell selection

According to one or more embodiments of the present invention, a delay circuit includes a first sub-circuit that delays a leading edge of an input signal according to first control settings, the input signal being for an electric device. The delay circuit further includes a second sub-circuit that delays a trailing edge of the input signal according to second control settings. An output signal from the delay circuit is received by the electric device.

Fine-grained programmable delay and pulse shaping circuit

A column access control circuit for generating column write enable outputs with redundancy steering control and bit write control for an integrated circuit chip, and an integrated circuit chip having the same. A column access control circuit may include: a column write enable driver, a redundancy steering logic, and a bit write controller. The column write enable driver may produce column write enable outputs through an output. The column write enable driver is configured to receive certain column interleave write enable and enable column write according to the column interleave write enable received. The redundancy steering logic is configured to receive one or more fuses and skip a damaged column indicated by a corresponding fuse. The bit write controller is configured to receive one or more bit write and provide bit write control according to the one or more bit write received.

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Poughkeepsie, NY, United States of America

Russell P Hayes