Alcatel USA Sourcing, L.p.

Alcatel

Russell L Humphrey

Long V Vo

Jose A Garcia

Robert S Gammenthaler, Jr

Michael J Hanlon

Michael A Vincze

A signaling link interface ( ) includes a high level data link controller ( ) that receives signaling information from network elements in a telecommunication network. A link state controller ( ) performs message transfer part level two processing on the signaling information. The link state controller ( ) generates a response message that the high level data link controller ( ) provides back to the network elements. The high level data link controller ( ) and the link state controller ( ) are implemented in hardware as field programmable gate array devices. Information related to operation of the signaling link interface ( ) may be downloaded from a remote site into the field programmable gate array devices. The signaling link interface ( ) processes signaling information received from a plurality of signaling links on a link by link basis.

Signaling link interface for processing signaling information in a telecommunications network

A system for interfacing with a data bus is provided. The system includes an egress bus data interface that can receive a single incoming stream of STM data and ATM data. The egress bus data interface transmits a single incoming stream of STM data, and a single incoming stream of ATM. The system also includes an ingress bus data interface. The ingress bus interface receives a single outgoing stream of STM data and a single outgoing stream of ATM data. The STM data and ATM data are transmitted in a single outgoing stream.

System and method for data bus interface

A system for selecting one of two or more parallel planes of data is provided. The system includes a first data buffer that is connected to a first data bus that carries a stream of datagrams. The first data buffer receives and stores datagrams from the first data bus. The system also includes a second data buffer that is connected to a second data bus that carries a stream of datagrams. The second data buffer receives and stores datagrams from the second data bus. A selection controller connected to the first data buffer and the second data buffer analyzes the datagrams stored in the first and second data buffers, and selects one of the datagrams to be the primary datagram.

System and method for plane selection

A data bus interface circuit is provided. The data bus interface circuit includes interface circuitry that can receive, store, and transmit data. Egress bus input circuitry is connected to the interface circuitry. The egress bus input circuitry receives incoming STM and ATM data from a first egress data bus. STM egress bus input circuitry is connected to the interface circuitry. The STM egress bus input circuitry transmits the incoming STM data over a second egress data bus. ATM egress bus input circuitry connected to the interface circuitry transmits the incoming ATM data over a third egress data bus. STM ingress bus input circuitry receives outgoing synchronous transfer mode data, and ATM ingress bus input circuitry receives outgoing asynchronous transfer mode data. Ingress bus output circuitry connected to the interface circuitry transmits outgoing STM and outgoing ATM data over a third ingress data bus.

Growing community of inventors

McKinney, TX, United States of America

Russell L Humphrey