Dell USA L P

Tandem Computers Incorporated

Compaq Computer Corporation, Inc.

Russell L Gillenwater

Philip John Brisky

Eric Hoxworth

Davoud Safari

Gary D Owens

Kenneth G Keels

A method and system for performing very high speed software downloads concurrent with system testing in an automated production environment and for test-sequencing in multi-tasking environments with consolidated automation and interactive operations are described. In one embodiment, during diagnostics and software download, a multi-tasking OS is booted on a target computer system, thereby enabling diagnostics to be run at the same time the software download is performed. A visual step-sequencing engine provides the ability to sequentially execute steps, as well as to execute steps in parallel and to combine parallel and sequential steps into loops. The sequencing engine provides a visual representation of the current run status of the target system in a Main window. The sequencing engine also integrates EMR debug tools into the same application so that EMR debug technicians can run failing steps directly from the application via an EMR Control window thereof and consolidates logs into a single location within the application viewable via a Logs window thereof.

System and method for sequencing and performing very high speed software downloads concurrent with system testing in an automated production environment

Method and system for performing very high speed software downloads concurrent with system testing in an automated production environment and for test-sequencing in multi-tasking environments with consolidated automation and interactive operations is described. In one embodiment, during diagnostics and software download, a multi-tasking OS is booted on a target computer system, thereby enabling diagnostics to be run at the same time the software download is performed. A visual step-sequencing engine provides the ability to sequentially execute steps, as well as to execute steps in parallel and to combine parallel and sequential steps into loops. The sequencing engine provides a visual representation of the current run status of the target system in a Main window. The sequencing engine also integrates EMR debug tools into the same application so that EMR debug technicians can run failing steps directly from the application via an EMR Control window thereof and consolidates logs into a single location within the application viewable via a Logs window thereof.

The real-time test controller maintains a failure database containing a history of past failures for devices under test and selectively sorts the history for the device to be tested. The diagnostic testing sequence is then rearranged with tests having higher failure rates being conducted first. If faults are detected, a message is provided to the operator and the failure database is either manually or automatically updated with the latest fault information. In this manner, a continuously updated history of faults is maintained and the most efficient testing sequence is followed, resulting in significant time and cost savings.

Real-time test controller

An application specific integrated circuit (ASIC) includes ASIC logic, test logic, dual function input test cells and dual function output test cells. The test logic with the input and output test cells provides manufacturing test capability for the ASIC logic with a plurality of input pins and a plurality of output pins while reducing both the gate count and signal time delay associated with the input and output test cells. Each input test cell includes a boundary scan circuit means and a built-in self-test circuit means. An input test cell has a signal propagation time delay for a signal, that travels from an input pin to an ASIC logic input line, equivalent to one two-to-one multiplexer signal propagation delay. Hence, while the input test cell has the capability of both built-in self-test and boundary scan testing, the dual capability is achieved without incurring a signal propagation time delay for each capability. Like the input test cells, each output test cell includes a boundary scan circuit means and a built-in self-test circuit means. The output test cell also has a signal propagation time delay for a signal, that travels from an ASIC logic output line to an output pin, equivalent to a single two-to-one multiplexer signal propagation delay.

Cell architecture for built-in self-test of application specific

An application specific integrated circuit (ASIC) includes ASIC logic and test logic that includes a fail-safe circuit and test logic circuitry. The test logic in conjunction with input and output test cells provides manufacturing test capability for the ASIC logic with a plurality of input pins and a plurality of output pins. The test logic generates several control signals that can affect operation of the ASIC logic. If any one of these signals is driven active by either a failure or a defect, the ASIC logic would be rendered inoperative. Consequently, each of these control signals is routed to the fail-safe circuit. These control signals include, for example, tri-state and reset signals and other control signals generated by test logic circuitry for the built-in testing of the ASIC. The fail-safe circuit generates a fail-safe control output signal for a corresponding control input signal from the test logic circuitry only during manufacturing testing when a fail-safe enable signal is applied to the fail-safe circuit. Preferably, the fail-safe enable signal is provided on one of the plurality of pins connected to the test logic so that the fail-safe enable signal cannot be generated by a failure or defect in the test logic circuitry.

Growing community of inventors

Round Rock, TX, United States of America

Russell L Gillenwater