Qualcomm Incorporated

Intel Corporation

Russell John Fagg

Charles E Wheatley, Iii

Joseph Patrick Burke

Chengzhi Pan

Christopher Hull

Dandan Li

A discrete time (DT) lowpass filter having various advantages is described. In an exemplary design, the DT lowpass filter includes a decimating DT filter (which may include a passive DT FIR filter and/or a passive DT IIR filter) and an active DT filter. The decimating DT filter receives a first DT signal at a first sample rate, filters and decimates the first DT signal by a factor of N, and provides a second DT signal at a second sample rate lower than the first sample rate. N may be greater than one. The active DT filter filters the second DT signal and provides a third DT signal at the second sample rate. A sampler samples a continuous time signal and provides the first DT signal. The sampler may further double the voltage of the first DT signal relative to the voltage of the continuous time signal.

Discrete time lowpass filter

Exemplary embodiments of the invention disclose receiver baseband filtering. In an exemplary embodiment, the filter device may comprise a continuous-time filter and a discrete-time filter operably coupled to the continuous time-filter. The discrete-time filter may include a passive infinite impulse response filter operably coupled between the continuous-time filter and an amplifier. The discrete-time filter may also include an active infinite impulse response filter operably coupled between an output of the amplifier and an input of the amplifier. The discrete-time filter may be configured to combine an output of the active infinite impulse response filter and an output of the passive infinite impulse response filter to form a composite signal. Furthermore, the amplifier may be configured to receive and amplify the composite signal.

Receiver filtering devices, systems, and methods

A frequency divider involves a plurality of Injection-locked Ring Oscillators (ILRO). A first ILRO includes a pair of cross-coupled N-channel transistors, a pair of load resistors, an integrating capacitor, and a current injection circuit. The drain of each transistor is coupled to the gate of the other transistor. Each load resistor couples the drain of each transistor to a circuit voltage source. The integrating capacitor couples the sources of each transistor. The current injection circuit alternately opens and closes a path from the source of each transistor to circuit ground in response to an oscillatory input signal of a first frequency. In response, the voltage state at the drain of each transistor is alternately latched and toggled, generating a differential pair of oscillating signals frequency divided by two. A first and second ILRO driven in antiphase generate two differential output signals in phase quadrature.

Divide-by-two injection-locked ring oscillator circuit

A discrete time receiver includes a low noise transconductance amplifier (LNTA), a discrete time sampler, a passive discrete time circuit, and a switched capacitor amplifier. The LNTA amplifies a received RF signal and provides an amplified RF signal. The discrete time sampler samples the amplified RF signal (e.g., with multiple phases of a sampling clock) and provides first analog samples. The passive discrete time circuit decimates and filters the first analog samples and provides second analog samples. The switched capacitor amplifier amplifies the second analog samples and provides third analog samples. The discrete time receiver may further include a second passive discrete time circuit, a second switched capacitor amplifier, and an analog-to-digital converter (ADC) that digitizes baseband analog samples and provides digital samples. The discrete time receiver can flexibly support different system bandwidths and center frequencies.

Discrete time receiver

An apparatus for wireless communications is disclosed including a signal generator adapted to generate a substantially periodic signal including a plurality of cycles, and a modulator adapted to modulate an amplitude, a phase or both the amplitude and the phase of the periodic signal on a per cycle basis. In one aspect, the modulator is adapted to modulate the amplitude, the phase, or both the amplitude and phase of the periodic signal with a defined modulation signal. In another aspect, the defined modulation signal includes a substantially root raised cosine signal. In yet another aspect, the defined modulation signal is configured to achieve a defined frequency spectrum for the modulated periodic signal.

Apparatus and method for modulating an amplitude, phase or both of a periodic signal on a per cycle basis

A frequency synthesizer with multiple tuning loops, e.g., a fine tuning loop and a coarse tuning loop, is described. The fine tuning loop may operate over a limited tuning range and may have fine frequency resolution. The coarse tuning loop may operate over a wide tuning range and may have coarse frequency resolution. The fine tuning loop may receive a reference signal at a reference frequency and generate a fine tuning signal at a first frequency adjustable in fine steps. The coarse tuning loop may receive the reference signal, generate an output signal at an output frequency, and generate a coarse tuning signal at a second frequency based on the output signal and the fine tuning signal. The second frequency may be adjustable in coarse steps, e.g., in integer multiples of the reference frequency. The output frequency may be determined based on the first frequency and the second frequency.

Frequency synthesizer with multiple tuning loops

Techniques for generating a differential output voltage between first and second output voltages that is double a differential input voltage between first and second input voltages. In one aspect, first and second capacitors of a constituent voltage doubler are charged to a differential input voltage during a charging phase. During an output phase non-overlapping in time with the charging phase, the first and second capacitors are stacked in series to generate the differential output voltage. The first and second capacitors are both coupled to a single common-mode voltage to provide a predefined common-mode output voltage. Further techniques for providing two or more constituent voltage doublers to extend the output phase are described.

Passive differential voltage doubler

A system and method of improving the power efficiency of a receiver for low duty cycle applications. In one aspect, the receiver includes a low noise amplifier (LNA) that is capable of being enabled in a relatively quick fashion so as to amplify an incoming signal when needed, and then being disabled to set the LNA in a low power consumption mode. In particular, the LNA includes a pair of complimentary devices, and an enable circuit adapted to quickly cause the complimentary devices to conduct substantially the same current. In another aspect, a bias voltage generating apparatus is provided that uses a residual voltage from a prior operation to establish the current bias voltage for the LNA. In particular, the apparatus includes a controller adapted to tune an adjustable capacitor to a capacitance based on a residual voltage applied to a fixed capacitor, and couple the capacitors together to establish the bias voltage.

System and method of using residual voltage from a prior operation to establish a bias voltage for a subsequent operation

An apparatus configured as a compandor to achieve a defined dynamic range for an output signal in response to an input signal. In particular, the apparatus comprises a first circuit adapted to generate a first signal from the input signal, wherein the first signal includes a first dynamic range (e.g., a first sensitivity and first compression point); and a second circuit adapted to generate a second signal from the input signal, wherein the second signal includes a second dynamic range (e.g., a second sensitivity and second compression point) that is different from the first dynamic range of the first signal. The apparatus may further include a third circuit adapted to generate an output signal related to a sum of the first and second signals. By adjusting the first and second dynamic ranges, an overall dynamic range for the output signal of the companding apparatus may be achieved.

System and method of companding an input signal of an energy detecting receiver

Techniques for generating quadrature signals from a local oscillator signal, wherein the generated quadrature signals have a frequency half of the local oscillator frequency. In an exemplary embodiment, two oscillators, e.g., injection locked oscillators, are provided, each oscillator having a load, a cross-coupled transistor pair, an integrating capacitor, and current injection transistors. A differential pair is coupled to the leads of each of the integrating capacitors, and the drains of the differential pair are coupled to the outputs of the other oscillator to help increase the slew rate of the output voltages of the other oscillator. The inputs to the differential pair may be first amplified to improve the gain of the differential pair. In another exemplary embodiment, the power consumption of the differential pair may be reduced by operating them in a discontinuous mode, e.g., by coupling the source voltages of the differential pair to corresponding delayed versions of the drain voltages.

Dynamic limiters for frequency dividers

A switched-capacitor decimator that can attenuate undesired signal components at odd harmonics of an output sample rate is described. In one design, the switched-capacitor decimator includes at least one sampling capacitor and multiple switches. For each sampling capacitor, the top plate is charged with a first input signal when the capacitor is selected for top charging, and the bottom plate is charged with a second input signal when the capacitor is selected for bottom charging. For each sampling capacitor, the top plate provides its stored charges to a first output signal and the bottom plate provides its stored charges to a second output signal when the capacitor is selected for reading. The switches couple the at least one sampling capacitor to the first and second input signals for charging and to the first and second output signals for reading.

Switched-capacitor decimator

An apparatus for generating an oscillating signal that includes a circuit to accelerate the time in which an oscillating signal reaches a defined steady-state condition from a cold start. The apparatus includes an oscillating circuit to generate an oscillating signal; a first circuit to supply a first current to the oscillating circuit; and a second circuit to supply a second current to the oscillating circuit, wherein the first and second currents are adapted to reduce the time duration for the oscillating signal to reach a defined steady-state condition. The apparatus may be useful in communication systems that use low duty cycle pulse modulation to establish one or more communications channels, whereby the apparatus begins generating an oscillating signal at approximately the beginning of the pulse and terminates the oscillating signal at approximately the end of the pulse.

Method and apparatus for generating oscillating signals

An apparatus for generating a pulse at a particular time dictated by an input. The apparatus may comprise an offset voltage generator for generating an offset voltage that is a function of the input, a current generator for generating a current, a ramp voltage generator for generating a ramp voltage having an initial value as a function of the offset voltage and a slope as a function of the current, and a pulse generator for generating a pulse in response to the ramp voltage reaching a threshold voltage. With this configuration, the time the pulse is generated is controlled by the input. This may be used in transceivers to control the time of transmission and the time of reception. Such times may be used to set up communication channels, such as ultra-wide band (UWB) channels, for communicating with other devices.

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San Diego, CA, United States of America

Russell John Fagg