Intel Corporation

Daedalus Prime LLC

Russell Jerome Fenger

Eliezer Weissmann

Eugene Gorbatov

Monica Gupta

Rajshree Chabukswar

Deepak Samuel Kirubakaran

Vijay Dhanraj

Travis T Schluessler

Efraim Rotem

Gaurav Khanna

David M Durham

Andrew J Herdrich

Alon Naveh

Dheeraj R Subbareddy

Guy M Therien

David A Koufaty

Ganapati Srinivasa

Hisham Abu Salah

Paolo L Narvaez

Mishali Naik

Inder M Sodhi

Devadatta V Bodas

Scott D Hahn

James Steven Burns

Baskaran Ganesan

Suresh Sugumar

Sundaravarathan R Iyengar

Paul Brett

Abirami Prabhakaran

Feranak Nelson

Mohan J Kumar

Victor B Lortz

James G Hermerding, Ii

Anil Aggarwal

Chee Lim Nge

Andrew D Henroid

Jianfang Olena Zhu

Zhongsheng Wang

Stephen T Chou

William A Braun

Raoul Rivas Toledano

Rajendra S Yavatkar

Nagabhushan Chitlur

Rinat Rappoport

Ahmad A Samih

Carol Bell

Sudheer Nair

John M Powell, Jr

Mil Travnicek

Chih-Kan Wang

Doron Rajwan

Ravishankar Iyer

Stephen H Gunther

Avinash N Ananthakrishnan

Ariel Gur

Shriharsha S Hegde

Balaji Masanamuthu Chinnathurai

Bret L Toll

Vedvyas Shanbhogue

Jason W Brandt

Hormuzd M Khosravi

Krishnakanth Venkata Sistla

Christian Maciocco

Atsuo Kuwahara

Ankush Varma

Stephen Anthony Fischer

James B Crossland

Ashok Raj

Vivek Garg

Bryant E Bigbee

Michael Mishaeli

Ahmad Yasin

Hsin-Yuo Liu

Asit K Mallick

Manasi Deval

Ashish V Choubal

Premanand Sakarda

Julius Yuli Mandelblat

Shaun M Conrad

Leena K Puthiyedath

Hisham Shafi

Yasser Rasheed

Kameswar Subramaniam

Hisham Abu-Salah

Marc D Torrant

Dheemanth Nagaraj

Muhammad Abozaed

Jianwei Dai

Amol Kulkarni

Shiv Kaushik

Israel Hirsh

Ashraf H Wadaa

Oron Lenz

Noor Mubeen

Arjan Van De Ven

Shadi T Khasawneh

Mukund Ramakrishna

Abhinav Karhu

Nir Misgav

Pankaj Parmar

Embodiments of apparatuses, methods, and systems for resource control based on software priority are described. In embodiments, an apparatus includes resource sharing hardware and multiple cores. The resource sharing hardware is to share the shared resource among the cores. A first core includes first execution circuitry to execute multiple threads. The first core also includes registers programmable by software. A first register is to store a first identifier of a first thread and a first priority tag to indicate a first priority of the first thread relative to a second priority of a second thread. A second register to store a second identifier of the second thread and a second priority tag to indicate the second priority of the second thread relative to the first priority of the first thread. The resource sharing hardware is to use the first priority and the second priority to control access to the shared resource by the first thread and the second thread.

Autonomous and extensible resource control based on software priority hint

A hardware and software coordinated processor power state policy (e.g., policy for C-state) that delivers optimal power state selection by taking in to account the performance and/or responsiveness needs of thread expected to be scheduled on the core entering idle, to achieve improved IPC and performance for cores running user critical tasks. The scheme provides the ability to deliver responsiveness gains for important and/or user-critical threads running on a system-on-chip. A power management controller coupled to the plurality of processing cores, wherein the power management controller receives a hint from an operating system indicative of a bias towards a power state or performance state for at least one of the processing cores of the plurality of processing cores based on a priority of a thread in context switch.

Hardware and software coordinated cost-aware low power state selection

In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

System, apparatus and method for dynamically adjusting platform power and performance based on task characteristics

An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.

Method, apparatus, and system for energy efficiency and energy conservation including power and performance balancing between multiple processing elements and/or a communication bus

A processor core energy-efficiency core ranking scheme akin to a favored core in a multi-core processor system. The favored core is the energy-efficient core that allows an SoC to use the core with the lowest Vfor energy-efficiency. Such Vvalues may be fused in appropriate registers or stored in NVM during HVM. An OS scheduler achieves optimal energy performance using the core ranking information to schedule certain applications on the core with lowest V. A bootstrap flow identifies a bootstrap processor core (BSP) as the most energy efficiency core of the SoC and assigns that core the lowest APIC ID value according to the lowest V. Upon reading the fuses or NVM, the microcode/BIOS calculates and ranks the cores. As such, microcode/BIOS calculates and ranks core APIC IDs based on efficiency around LFM frequencies. Based on the calculated and ranked cores, the microcode or BIOS transfers BSP ownership to the most efficiency core.

Energy-efficient core voltage selection apparatus and method

Systems, apparatuses and methods may provide for technology that automatically determines a runtime performance of a plurality of heterogeneous processing units based on system-level thread characteristics, wherein the runtime performance is determined on a per performance class basis. The technology may also automatically determine a runtime energy efficiency of the heterogeneous processing units, wherein the runtime energy efficiency is determined on a per efficiency class basis. In one example, technology selectively unparks one or more of the heterogeneous processing units based on the runtime performance and the runtime energy efficiency.

Hardware directed core parking based on performance and energy efficiency capabilities of processing units and runtime system characteristics

Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

Apparatuses, methods, and systems for hardware control of processor performance levels

The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.

Operating system assisted prioritized thread execution

A data processing system comprises a hybrid processor comprising a big TPU and a small TPU. At least one of the TPUs comprises an LP of a processing core that supports SMT. The hybrid processor further comprises hardware feedback circuitry. A machine-readable medium in the data processing system comprises instructions which, when executed, enable an OS in the data processing system to collect (a) processor topology data from the hybrid processor and (b) hardware feedback for at least one of the TPUs from the hardware feedback circuitry. The instructions also enable the OS to respond to a determination that a thread is ready to be scheduled by utilizing (a) an OP setting for the ready thread, (b) the processor topology data, and (c) the hardware feedback to make a scheduling determination for the ready thread. Other embodiments are described and claimed.

Technology for optimizing hybrid processor utilization

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of logical processors including comprising one or more of a first logical processor type and a second logical processor type, the first logical processor type associated with a first core type and the second logical processor type associated with a second core type; a scheduler to schedule a plurality of threads for execution on the plurality of logical processors in accordance with performance data associated with the plurality of threads; wherein if the performance data indicates that a new thread should be executed on a logical processor of the first logical processor type, but all logical processors of the first logical processor type are busy, the scheduler to determine whether to migrate a second thread from the logical processors of the first logical processor type to a logical processor of the second logical processor type based on an evaluation of first and second performance values associated with execution of the first thread on the first or second logical processor types, respectively, and further based on an evaluation of third and fourth performance values associated with execution of the second thread on the first or second logical processor types, respectively.

Apparatus and method for adaptively scheduling work on heterogeneous processing resources

A data processing system with technology for dynamically grouping threads includes a machine-readable medium and first and second cores, each with multiple logical processors (LPs). The system also comprises an operating system which, when executed, enables the system to select an LP to receive a new low-priority thread and to assign the new low-priority thread to the selected LP. The operation of selecting an LP to receive the new low-priority thread comprises, when the first core has multiple idle LPs, automatically determining whether the second core has an idle LP and a busy LP that is executing a current low-priority thread. In response to determining that the second core has an idle LP and a busy LP that is executing a current low-priority thread, the system automatically selects the idle LP in the second core to receive the new low-priority thread. Other embodiments are described and claimed.

Technology for dynamically grouping threads for energy efficiency

In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.

Utilization metrics for processing engines

Techniques and apparatus for managing performance states of processing circuitry of a computing device are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processing circuitry, and logic, at least a portion of comprised in hardware coupled to the at least one processing circuitry, to set a first performance state (P-state) of the at least one processing circuitry based on system utilization information, access a performance interface element comprising a plurality of performance metric hints, update the first P-state to a second P-state responsive to one of the plurality of performance metric hints being set by an operating system (OS) of the apparatus, and maintain the first P-state responsive to none of the plurality of performance metric hints being set by the operating system (OS). Other embodiments are described and claimed.

Techniques for controlling processor performance states

Growing community of inventors

Beaverton, OR, United States of America

Russell Jerome Fenger