Intel Corporation

Russell J Wunderlich

Dimitrios Ziakas

Chih-Cheh Chen

Tina C Zhong

Thi Dang

Vincent J Zimmer

Mohan J Kumar

Krishnakanth Venkata Sistla

Murugasamy K Nachimuthu

Mallik Bulusu

David W Grawrock

Robert Charles Swanson

Mahesh S Natu

Stephen S Pawlowski

Kirk D Brannock

Madhusudhan Rangarajan

Ramamurthy Krithivas

Bruce Querbach

Malay Trivedi

Bassam N Coury

Tieyu Zheng

James Steven Burns

Keshavan K Tiruvallur

Mark B Trobough

Chinna B Prudvi

Hermann Gartler

Vui Yong Liew

Eswaramoorthi Nallusamy

Anand K Enamandram

Ashok N Kabadi

Samie B Samaan

Keith A Drescher

Robert W Cone

Jay Joseph Nejedlo

Mukesh Kataria

Lyle E Cool

James J Grealish

Abhijit Davare

Brian Meyer

C Brendan Traw

Babak B Nikjou

Priyadarsan Patra

Ridvan A Sahan

Rahima K Mohammed

William Penner

Wee Hoo Cheah

Yuen Tat Lee

John L Baudrexl

John R Lindsley

Arun R Ramadorai

Miles F Schwartz

Kapila B Udawatta

Loren James McConnell

Kip C Killpack

Kyle Markley

Christian E Iovin

Travis K Goff

Evan J Halprin

Jiun Long Foo

Selvakumar Raja Gopal

Neil Dobler

Nagib Z Hakim

Timothy S Storey

Yi Amy Xia

Edwin E Parks

Padmakumar Gopal

Sanjay S Salem

David C Florey

Jagannath Coimbatore Premkumar

Examples include techniques to collect crash data for a computing system following a catastrophic error. Examples include a management controller gathering error information from components of a computing system that includes a central processing unit (CPU) coupled with one or more companion dice following the catastrophic error. The management controller to gather the error information via a communication link coupled between the management controller, the CPU and the one or more companion dice.

Techniques to collect crash data for a computing system

Examples may include chipsets, processor circuits, and a system including chipsets and processor circuits. The chipsets and processor circuits can be coupled together via side band interconnect. The chipsets and processor circuits can be coupled together dynamically, during runtime using the side band interconnects. A chipset can send control signals for other chipsets and/or receive control signals from processor circuits via the side band links to dynamically coordinate the chipsets and processor circuits into systems.

External resource discovery and coordination in a data center

Embodiments disclosed herein relate to coordinated system boot and reset flows and improve reliability, availability, and serviceability (RAS) among multiple chipsets. In an example, a system includes a master chipset having multiple interfaces, each interface to connect to one of a processor and a chipset, at least one processor connected to the master chipset, at least one non-master chipset connected to the master chipset, and a sideband messaging channel connecting the master chipset and the non-master chipsets, wherein the master chipset is to probe a subset of its multiple interfaces to discover a topology of connected processors and non-master chipsets, and use the sideband messaging channel to coordinate a synchronized boot flow.

Method to coordinate system boot and reset flows and improve reliability, availability and serviceability (RAS) among multiple chipsets

Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.

Method and apparatus for server platform architectures that enable serviceable nonvolatile memory modules

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

Test, validation, and debug architecture

Platform controller, computer-readable storage media, and methods associated with initialization of a computing device. In embodiments, a platform controller may comprise a boot controller and one or more non-volatile memory modules, coupled with the boot controller. In embodiments, the one or more non-volatile memory modules may have first instructions and second instructions stored thereon. The first instructions may, when executed by a processor of a computing device hosting the platform controller, cause initialization of the computing device. The second instructions, when executed by the boot controller, may cause the boot controller to monitor at least a portion of the execution of the first instructions by the computing device and may generate a trace of the monitored portion of the execution of the first instructions. In embodiments, the trace may be stored in the one or more non-volatile memory modules. Other embodiments may be described and/or claimed.

Initialization trace of a computing device

Methods, apparatuses, and systems may provide a sensor to monitor a power consumption of a non-volatile random access memory (RAM) and a volatile RAM. A switch, connected to an output of the sensor, controls power to the non-volatile RAM, and a voltage regulator regulates a voltage of the non-volatile RAM and the volatile RAM. One or more memory slots receive the non-volatile RAM and the volatile RAM, and a processor receives information from the sensor, and controls the voltage regulator based on the received information. The voltage regulator comprises a plurality of registers to store power consumption information of the non-volatile RAM and the volatile RAM.

Power management in dual memory platforms

Growing community of inventors

Livermore, CO, United States of America

Russell J Wunderlich