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Siemens Aktiengesellschaft

Infineon Technologies Ag

Russell J Houghton

William R Tonti

Claude Louis Bertin

John Atkinson Fifield

Christopher P Miller

Jack Allan Mandelman

Louis L Hsu

Ramachandra Divakaruni

Erik L Hedberg

Wilbur David Pricer

Rajiv V Joshi

Wayne Frederick Ellis

Duane E Galbi

Adam B Wilson

Max Gerald Levy

Steven William Tomashot

Timothy Dooling Sullivan

Thomas M Maffitt

Jeffrey H Dreibelbis

Mark David Jacunski

Richard Michael Parent

Rick L Mohler

Nicholas Martin Van Heel

Wayne M Trickle

Jeffrey P Gambino

Thomas Vogelsang

Martin Brox

Robert H Dennard

Helmut Schneider

John Kenneth DeBrosse

Li-Kong Wang

John E Gersbach

Wing Kin Luk

Badih El-Kareh

Ciaran J Brennan

Kevin McStay

Roy Childs Flaker

Sabine Kieser

Michael A Killian

Alan D Norris

W David Pricer

Michael P Clinton

Ernst J Stahl

Oliver Weinfurtner

Josef T Schnell

Klaus G F Enk

Joni C Hsu

Toshiaki Kirihara

Azzouz Nezar

A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the substrate and said electrode of said second device, said second insulator having a second value of said given characteristic that is different from said first value. The electrodes of the diode and the FET are coupled to one another, and a source of programming energy is coupled to the diode to cause it to permanently decrease in resistivity when programmed. The programmed state of the diode is indicated by a current in the FET, which is read by a sense latch. Thus a small resistance change in the diode translates to a large signal gain/change in the latch. This allows the diode to be programmed at lower voltages.

Method of forming a high impedance antifuse

An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.

Method of forming connection and anti-fuse in layered substrate such as SOI

A semiconductor memory having at least one memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device controlled by a control signal. The invention also relates to a tri-state driver device for driving the control signal. Further, there is a method for operating a memory, in which the memory has a memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device controlled by a control signal.

Semiconductor memory having tri-state driver device

High impedance antifuse

Structures and methods of anti-fuse formation in SOI

A combined low-voltage, low-power band-gap reference and temperature sensor circuit is provided for providing a band-gap reference parameter and for sensing the temperature of a chip, such as an eDRAM memory unit or CPU chip, using the band-gap reference parameter. The combined sensor circuit is insensitive to supply voltage and a variation in the chip temperature. The power consumption of both circuits, i.e., the band-gap reference and the temperature sensor circuits, encompassing the combined sensor circuit is less than one &#x3bc;W. The combined sensor circuit can be used to monitor local or global chip temperature. The result can be used to (1) regulate DRAM array refresh cycle time, e.g., the higher the temperature, the shorter the refresh cycle time, (2) to activate an on-chip or off-chip cooling or heating device to regulate the chip temperature, (3) to adjust internally generated voltage level, and (4) to adjust the CPU (or microprocessor) clock rate, i.e., frequency, so that the chip will not overheat. The combined band-gap reference and temperature sensor circuit of the present invention can be implemented within battery-operated devices having at least one memory unit. The low-power circuits of the sensor circuit extend battery lifetime and data retention time of the cells of the at least one memory unit.

Low-power band-gap reference and temperature sensor circuit

A method for sensing data stored within a cross point magnetic random access memory (MRAM) device includes establishing an offset voltage of a sense amplifier, the sense amplifier selectively coupled to a selected bitline within the MRAM device, the selected bitline being in communication with an MRAM cell to be read. A read current is applied through the MRAM cell to be read, and a reference current is applied through the selected bitline. A signal voltage is sensed on the selected bitline, the signal voltage being generated in response to the read current and the reference current. The signal voltage is coupled to an input of the sense amplifier, wherein the sense amplifier provides an offset corrected output reflective of the data state of the MRAM cell.

Capacitively coupled sensing apparatus and method for cross point magnetic random access memory devices

Method for forming a first one time, voltage programmable logic element in a semiconductor substrate of first conductivity type, forming a first layer beneath a surface of the substrate, the first layer having a second conductivity type. A trench is formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench.

Method for forming a voltage programming element

A method and structure for forming an emitter in a vertical bipolar transistor includes providing a substrate having a collector layer and a base layer over the collector layer, forming a patterning mask over the collector layer, and filling openings in the mask with emitter material in a damascene process. The CMOS/vertical bipolar structure has the collector, base regions, and emitter regions vertically disposed on one another, the collector region having a peak dopant concentration adjacent the inter-substrate isolation oxide.

Logic SOI structure, process and application for vertical bipolar transistor

An apparatus and method for wordline voltage compensation in integrated memories is provided, where the apparatus includes an array threshold voltage (&ldquo;V &rdquo;) monitor, a wordline on voltage (&ldquo;V &rdquo;) generator in signal communication with the threshold voltage monitor for providing a wordline on voltage responsive to a change in the monitored array threshold voltage, and a wordline off voltage (&ldquo;V &rdquo;) generator in signal communication with the threshold voltage monitor for providing a wordline off voltage responsive to a change in the monitored array threshold voltage; and where the corresponding method for compensating each of a wordline on signal and a wordline off signal in correspondence with an array threshold signal includes monitoring an array threshold signal, generating a wordline on signal responsive to the monitored array threshold signal, and generating a wordline off signal responsive to the monitored array threshold signal.

Wordline on and off voltage compensation circuit based on the array device threshold voltage

A centralized power supply system for a multi-system on chip device includes: an external power supply for supplying power to the device; a centralized DC generator macro having generator components for receiving the external power supplied and generating therefrom one or more power supply voltages for use by surrounding system macros provided on the multi-system chip, the centralized DC generator macro further distributing the generated power supply voltages to respective system macros. A noise blocking structure is provided that surrounds the centralized DC generator system and isolates the centralized DC generator system from the surrounding system macros.

Integrated power solution for system on chip applications

A DC analog circuit which monitors a DRAM sample cell access device and outputs a DC reference voltage to the word line voltage regulation system. The resulting output voltage V from the word line voltage regulation system will then vary in accordance with the cell access device parametrics so as to guarantee a full high level will always be written into the DRAM cell.

DRAM word line voltage control to insure full cell writeback level

A compensated driver for maintaining constant impedance during data transfer from an integrated circuit comprises an output portion having an output device to transfer data from the integrated circuit and a mimic circuit portion having a sample output device scaled to a fraction of the output device adapted to accept a reference current and generate a sample voltage. A mimic circuit portion has a sample output device scaled to a fraction of the output device adapted to accept a reference current and generate a sample voltage. A differential amplifier portion is adapted to generate a control voltage in response to a reference voltage and the sample voltage. A predrive portion applies either a ground or the predetermined control voltage from the differential amplifier portion to the output stage portion in response to an input, the control voltage regulating the output device in the output stage portion to achieve a more constant impedance.

Constant impedance driver for high speed interface

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Essex Junction, VT, United States of America

Russell J Houghton