Lsi Logic Corporation

Lsi Corporation

Russell J Henry

Bret S Weber

Dennis E Gates

Keith W Holt

John R Kloeppner

Mohamad H El-Batal

Gerald James Fredin

Charles E Nichols

Robert E Stubbs

Max L Johnson

Roger Hickerson

James K Sandwell

Scott Masterson

The present invention is a system for implementing a storage protocol with initiator controlled data transfer including a host device, a target device and an intermediate device, the intermediate device for communicatively coupling the host device and the target device. The intermediate device is configured to control a data transfer phase of an input/output (I/O) between said intermediate device and said target device.

System and method for implementing a storage protocol with initiator controlled data transfer

The present invention is a system utilizing multicast with distributed intelligence including an initiator device for transmitting a request, the request being addressed to a multicast group. The system also includes a switch for receiving the request from the initiator device. The switch is configured with multicast functionality for multicasting copies of the request to the multicast group. Additionally, the system includes a plurality of multicast group devices, each configured for receiving a copy of the request from the initiator device, via the switch. Each device of the plurality of multicast group devices is further configured with mapping functionality for allowing the storage device to determine a storage layout of the multicast group device. The initiator device, switch and each device of the plurality of multicast group devices are communicatively coupled via a network.

System & method for fabric storage utilizing multicast with distributed intelligence

Systems and methods for reducing or eliminating use of read transactions by a message consuming device coupled through a shared bus to a message producing device to transfer a message from the producing device to the consuming device. Features and aspects hereof provide for use of only write transactions on the bus issued by the devices to transfer messages directly into the data memory of the consuming device. A memory manager on the producing device may manage allocation and freeing of buffer space within the data memory of the consuming device. The producing device notifies the consuming device when a message transfer is completed.

Methods and systems for interprocessor message exchange between devices using only write bus transactions

A multiple-processor system and boot procedure are provided. The system includes an integrated circuit having first and second embedded processors. A volatile memory and a non-volatile memory are shared by the first and second processors. The non-volatile memory includes a set of boot load instructions executable by the first and second processors.

Method and apparatus for booting independent operating systems in a multi-processor core integrated circuit

Apparatus, systems and methods for clustering multiple PCI Express hierarchies to enable access of components in different hierarchies. Each PCI Express hierarchy includes a root device as well as a cluster port for coupling each hierarchy to each other hierarchy of a physical cluster through a PCI Express switched fabric. Memory addresses and transaction IDs are re-mapped by the cluster port of each hierarchy to partition the PCI Express space of the system of multiple hierarchies. A first portion of the partitioned space is reserved for access to local components within a hierarchy. A second portion of the space is used to access remote components of other hierarchies from within a different first hierarchy. The address and transaction ID values exchanged in such remote transactions are re-mapped and used by the cluster port of each hierarchy to route exchanges between hierarchies using standard PCIe root devices, endpoint devices, and switches.

Apparatus and methods for clustering multiple independent PCI express hierarchies

Methods and systems for end-to-end data protection in a computer are disclosed. A data integrity field is generally associated with data transferred along a data path in a computer. A virtual end-to-end address can be established, which is associated with the data integrity field, wherein the virtual end-to-end address transfers encoded information to a controller of the computer through one or more addresses of a read and/or write request thereof. The encoded information can be utilized to identify an offending entity within the data path. An end-to-end access list can also be associated with the virtual end-to-end address, such that the end-to-end access list contains at least one entry for every data transfer request provided to an interface device. Data corruption is therefore preventable in the entire I/O path in a computer from a host bus adapter through to the actual physical drive.

Methods and systems for end-to-end data protection in a memory controller

A method and system for facilitating communication between computer subnets are provided. One embodiment of the present invention comprises presetting buffers in an internal subnet, wherein the buffers help route external commands to a plurality of devices within the internal subnet. When a command from an external subnet is received by the internal subnet, the command is translated and sent to the proper internal device, as determined by the buffers. The command is then performed by the proper internal device. In another embodiment of the present invention, translation mapping are established for the internal subnet. When a command is received from an external subnet, the destination address associated with the command is translated to the address of the appropriate internal device, and the command is then sent directly to the internal device, which performs the command. By using either the buffer or translation mappings, the internal subnet appears to be a single device to the external subnet.

Infiniband isolation bridge merged with architecture of an infiniband translation bridge

Systems and methods for handling I/O requests from a host system to a storage system. A system includes an I/O module for processing I/O requests from a host system, a virtualized storage element, and a communication medium coupling the I/O module to the virtualized storage elements. The virtualized storage element includes a mapping table for translating virtual storage locations into physical storage locations and a plurality of physical storage locations. The virtualized storage element generates base virtual addresses using the mapping table to communicate the base virtual addresses to the I/O module. The I/O module generates specific virtual addresses using the base virtual addresses and using information derived from the I/O requests. The I/O module uses the specific virtual addresses in communication with the virtualized storage element to identify the physical storage locations in the virtualized storage element.

Method and apparatus for handling storage requests

A hardware assisted searching mechanism is provided that offloads the processor from searching operations. In a preferred embodiment, the hardware assisted searching mechanism performs a binary search of an associated 32 bit register against a binary search table that is set up by the firmware of the storage system. From this binary search table, an index into other structures stored in firmware is obtained that may be used to identify a target device. For example, when a search is to be performed due to receipt of an I/O operation, the firmware, i.e. software instructions stored in the persistent memory chip that are executed by the system processor, writes a 32 bit value to a hardware register that is used by the hardware assisted searching mechanism of the present invention. The hardware assisted searching mechanism performs a binary search of a binary search table based on the contents of the hardware register and returns an index of the entry in another hardware register. This index is then used to index into a storage device mapping structure stored in the firmware that are indexed in the same manner as the binary search table. The index provides a starting point in the storage device mapping structure and from this starting point, the logical unit number is used to identify a particular storage array and logical unit number for the destination of the I/O operation.

Method and apparatus for performing a high speed binary search in time critical environments

Systems and methods for generating, maintaining, and using merged partitions to process requests of one or more host systems to storage partitions of one or more storage elements. Each merged partition maps to one or more storage partitions defined within one or more of the storage elements. The storage elements may be combined to form a storage complex. Each storage element of the storage complex may include one or more storage volumes, such as an array of storage volumes. A system includes a map processor and an interface controller. The map processor is configured for mapping the storage partitions of each storage element to generate one or more merged partitions. The interface controller is communicatively connected to the host systems and to the map processor for processing the requests of the host systems to the storage volumes based on the merged partitions.

Method and apparatus for mapping storage partitions of storage elements to host systems

System and methods for managing requests of a host system to physical storage partitions. A storage system includes a plurality of storage elements with each storage element configured for providing data storage. A communications switch is communicatively connected to the storage elements for transferring requests to the physical storage partitions. A host system includes a storage router for mapping a portion of the physical storage partitions to logical storage partitions such that the host system can directly access the portion via the requests. Each of the storage elements includes a storage controller configured for processing the requests of the host system. The storage elements also include any of a disk storage device, tape storage device, CD storage device, and a computer memory storage device.

Method and apparatus for mapping storage partitions of storage elements for host systems

Methods and associated structure for improving storage system performance by reducing latency associated with communication medium transactions internal to a storage subsystem. In one aspect of the present invention, an I/O control element associated with a storage system transmits prefetch read requests to an associated storage element of the storage system in response to receipt of a host system request. This allows the storage element to commence data transfer to the I/O element in advance of the I/O element returning the data to the host system. Subsequent transfers of data from the storage element to the I/O element then overlap the transfer of data from the I/O element to the host. In another specific aspect of the present invention, methods and associated structures eliminate latency associated with PCI-X bus split transactions between the front-end (host interface portion) of the I/O element and the back-end (storage element interface) of the I/O element by overlapping the transfer of prefetched data to the host system with continued fetching of subsequent data from the storage element.

Method and structure for read prefetch in a storage complex architecture

A method of increasing computer system bandwidth for computer system having two or more memory complexes is disclosed in which exclusive OR operations are performed on the data from the data regions to generate parity information which is stored in the same single cache pool as the data regions. By using a single cache pool for related data regions, bandwidth and performance are improved.

Multiple memory system support through segment assignment

The present invention is directed to a host interface bypass on a fabric based array controller. An apparatus of the present invention may include an external electronic device suitable for performing a function, a controller and a fabric connection. The controller includes at least one internal module, the internal module providing a controller function. The fabric connection communicatively connects the external device to the controller, wherein the module of the controller is directly accessible by the external electronic device.

Host interface bypass on a fabric based array controller

The present invention is directed to a system and method for eliminating race conditions in RAID controllers while utilizing a high bandwidth internal architecture for data flow. A remote memory controller of the present invention may ensure that an acknowledge signal is sent only after a memory operation has been actually completed. This may provide for remote direct memory access without coherency problems and data corruption problems while a high bandwidth data flow internal architecture is being utilized.

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Wichita, KS, United States of America

Russell J Henry