Exar Corporation

Ampere Computing LLC

Qimonda Ag

Siemens Aktiengesellschaft

Russell Homer

Alfred Yeung

Khai Hoan Duong

Abhiram Saligram Chandrashekar

Hamid Partovi

Luca Ravezzi

Helmut Brazdrum

Techniques efficiently assist in performing write operations in memories with resistive bit lines. A memory can comprise memory cells associated with respective word lines and bit lines. A write assist component can be associated with a subset of the memory cells associated with a bit line. Configuration of the write assist component can be based on the type of transistors employed by write circuits associated with the memory cells. During a write operation, the write assist component adds an additional current path to the ground, or the power supply, or both, at or in proximity to the far end of the write bit line when an appropriate write polarity is applied to the bit line by the driver at the other end of the bit line. This mitigates the effects of resistance of the bit line, which mitigates IR loss of the write signal.

Write assist for memories with resistive bit lines

One embodiment provides an integrated circuit including a first circuit, a second circuit, and a third circuit. The first circuit is configured to provide a calibrated signal. The second circuit is configured to low pass filter the calibrated signal and provide a filtered calibrated signal. The third circuit is configured to provide a control signal and store the control signal based on the filtered calibrated signal. The third circuit averages stored controlled signals to provide a calibration result.

Integrated circuit including calibration circuit

A communications system comprising a segmenting mechanism configured to receive a plurality of payloads and divide each of the received payloads into segments, a framing mechanism configured to insert at least one of the segments from each of the plurality of payloads into a packet, a first interface configured to transmit the packet, and a second interface configured to transmit segment information about the segments in the packet.

Communications system with segmenting and framing of segments

A communications system comprising a first stage including a first scan table and a second stage including a second scan table. The first stage is configured to select a first channel identification from the first scan table and provide data from a channel identified by the first channel identification. The second stage is configured to receive the data and select a second channel identification from the second scan table to provide the received data at essentially a data rate of the channel on a synchronous network.

Growing community of inventors

Los Gatos, CA, United States of America

Russell Homer