International Business Machines Corporation

Kabushiki Kaisha Toshiba

Globalfoundries Inc.

Russell Herbert Arndt

Glenn Walton Gale

Ravikumar Ramachandran

John Anthony Fitzsimmons

David Lee Rath

Charles Jesse Taft

Frederick William Kern, Jr

Rosa A Orozco-Teran

Kenneth John Giewont

Harald F Okorn-Schmidt

Kenneth T Settlemyer, Jr

Ryan Wayne Wuthrich

Karen P Madden

Paul F Findeis

George Francis Ouimet, Jr

Dario Salgado

Kangguo Cheng

Yun Yu Wang

Fee Li Lie

Hong He

Babar Ali Khan

Muthumanickam Sankarapandian

Gauri V Karve

Byeong Yeol Kim

Xinhui Wang

Hiroyuki Akatsu

Anthony Gene Domenicucci

Soichi Nadahara

Xi Li

Jinghong Li

William Alfred Syverson

M Dean Sciacca

Jin J Wu

Bradley Paul Jones

Susan L Cohen

Richard O Henry

Michael Joseph MacDonald

David F Hilscher

James Hannah

Kevin E Mello

George F Ouimet, Jr

Craig M Ransom

Michael Robert Biagetti

Judith A Coffin

Robert J MacHugh

Brian E Johnson

Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a semiconductor structure having a first metal layer and a plurality of dielectric layers on top of the first metal layer; creating one or more openings through the plurality of dielectric layers to expose the first metal layer underneath the plurality of dielectric layers; causing the one or more openings to expand downward into the first metal layer and expand horizontally into areas underneath the plurality of dielectric layers; applying a layer of lining material in lining sidewalls of the one or more openings inside the plurality of dielectric layers; and filling the expanded one or more openings with a conductive material.

Self aligned contact structure

Self-aligned contact structure

A method for protecting channels during fin fabrication. Fins are formed on a substrate. A conformal liner layer (or layers) is applied on the fins. Active portions of a semiconductor device are patterned in the fins using a first organic planarizing material. The first organic planarizing material is stripped. The length of the fins is adjusted using a second organic planarizing material. The second organic planarizing material is stripped. The conformal liner layer(s) is stripped.

Channel protection during fin fabrication

A method including forming a deep trench in a semiconductor-on-insulator substrate including an SOI layer directly on top of a buried oxide layer directly on top of a base substrate, masking only a top surface of the SOI layer and a sidewall of the SOI layer exposed within an upper portion of the deep trench with a dielectric material without masking any surface of the base substrate exposed within a lower portion of the deep trench, and forming a bottle shaped trench by etching the base substrate exposed in the lower portion of the deep trench selective to the dielectric material and the buried oxide layer.

Wet bottling process for small diameter deep trench capacitors

An etching method. The method includes etching a first plurality of silicon wafers in a first enchant, each silicon wafer having SiOand SiNdeposited thereon, where the etching includes dissolving a quantity of the SiOand a quantity of the SiNin the first etchant. A quantity of insoluble SiOprecipitates. A ratio of a first etch rate of SiNto a first etch rate of SiOis determined to be less than a predetermined threshold. A portion of the first etchant is combined with a second etchant to form a conditioned etchant. A second plurality of silicon wafers is etched in the conditioned etchant. A ratio of a second etch rate of SiNto a second etch rate of SiOin the conditioned etchant is greater than the threshold. A method for exchanging an etching bath solution and a method for forming a selective etchant are also disclosed.

Selective etching bath methods

A tool and method is provided for mixing multiple components and feeding a single blend of the multiple components into the tool. The method includes adjusting a concentration of etchant solution. The method includes determining an etch target for each batch of wafers of a plurality of batches of wafers entering an etch chamber of a wafer processing tool. The method further includes adjusting a concentration of 40% NHF to 49% HF for the each batch of wafers of the plurality of batches of wafers entering the wafer processing tool during a single run.

Tool for manufacturing semiconductor structures and method of use

An etching method. The method includes etching a first plurality of silicon wafers in a first enchant, each silicon wafer having SiOand SiNdeposited thereon, where the etching includes dissolving a quantity of the SiOand a quantity of the SiNin the first echant. A quantity of insoluble SiOprecipitates. A ratio of a first etch rate of SiNto a first etch rate of SiOis determined to be less than a predetermined threshold. A portion of the first etchant is combined with a second etchant to form a conditioned etchant. A second plurality of silicon wafers is etched in the conditioned etchant. A ratio of a second etch rate of SiNto a second etch rate of SiOin the conditioned etchant is greater than the threshold. A method for exchanging an etching bath solution and a method for forming a selective etchant are also disclosed.

In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material. The trench has an initial lateral dimension in a first direction transverse to the vertical direction. The semiconductor material exposed at the surface of the trench then is etched in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface. A dopant-containing liner may then be deposited to line the surface of the trench and a temperature of the substrate then be elevated to drive a dopant from the dopant-containing liner into the semiconductor region adjacent to the surface. During such step, typically a portion of the semiconductor material exposed at the wall is oxidized. At least some of the oxidized portion is removed to expose a wall of an enlarged trench, along which wall a dielectric layer and conductive material are formed in order to form a trench capacitor.

Bottle-shaped trench capacitor with enhanced capacitance

A method of batching substrates in an automated processing tool, the automated process tool and a system for batching substrates in the automated process tool. The method includes selecting a first container containing a first group of substrates; simultaneously transferring each substrate of the first group of substrates into a batching station of the automated processing tool; selecting a second container containing a second group of substrates; selecting less than all substrates of the second group of substrates; and transferring each substrate of the less than all substrates of the second group of substrates to the batching station to form a third group of substrates.

Method for creating wafer batches in an automated batch process tool

Methods for selective salicidation of a semiconductor device. The invention implements a chemical surface pretreatment by immersion in ozonated water HO prior to metal deposition. The pretreatment forms an interfacial layer that prevents salicidation over an n-type structure. As a result, the invention does not add any additional process steps to the conventional salicidation processing.

Selective salicidation methods

Disclosed is a method of removing liquid from a surface of a semiconductor wafer that comprises the steps of providing a plurality of capillary channels, each said capillary channel having a first opening and a second opening, and then placing said first openings in contact with the liquid in a manner effective in drawing away the liquid by capillary action.

Capillary dry process and apparatus

A method of removing water from the surface of a silicon wafer or other substrate subjected to wet processing which includes a step of water rinsing. In this method a silicon wafer whose surface includes liquid water is disposed in an atmosphere saturated with water vapor. The water vapor is removed from the surface of the silicon wafer by a stream of water-saturated gas. Upon removal of liquid water from the surface of the silicon wafer the water vapor in the water vapor saturated atmosphere is removed by evaporation.

Method of drying substrates

A method for preparing a semiconductor material for formation of a silicide layer on selected areas thereupon is disclosed. In an exemplary embodiment of the invention, the method includes removing at least one of a nitride and an oxynitride film from the selected areas, removing metallic particles from the selected areas, removing surface particles from the selected areas, removing organics from the selected areas, and removing an oxide layer from the selected areas.

Method for improved fabrication of salicide structures

Semiconductor substrates are contacted with a deionized water solution containing an acidic material.

Process for treating a semiconductor substrate

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Fishkill, NY, United States of America

Russell Herbert Arndt