Patriot Scientific Corporation

Nanotronics Corporation

Other

Viametrix Inc.

Russell H Fish, Iii

Charles H Moore

In one aspect, the invention comprises a thread optimized multiprocessor prepared by a semiconductor manufacturing process, comprising the steps of: (a) interconnecting less than 4 layers of metal on at least one die; (b) embedding at least one processor in said at least one die; and (c) mounting said at least one die on a dual inline memory module.

Thread optimized multiprocessor architecture

In one aspect, the invention comprises a system comprising: (a) a plurality of parallel processors on a single chip; and (b) computer memory located on the chip and accessible by each of the processors; wherein each of the processors is operable to process a de minimis instruction set, and wherein each of the processors comprises local caches dedicated to each of at least three specific registers in the processor. In another aspect, the invention comprises a system comprising: (a) a plurality of parallel processors on a single chip; and (b) computer memory located on the chip and accessible by each of the processors, wherein each of the processors is operable to process an instruction set optimized for thread-level parallel processing.

A technique for organizing a plurality of computers such that message broadcast, content searching, and computer identification of the entire collection or a subset of the entire collection may be performed quickly without the use of a controlling computer. The technique describes the creation, operation, and maintenance of a connection scheme by which each computer in the collection appears to be the top level of a hierarchical array. The maintenance of this hierarchical connection scheme allows one to many communications throughout the collection of computers to scale geometrically rather than linearly.

Distributed means of organizing an arbitrarily large number of computers

A microprocessor integrated circuit including a processing unit disposed upon an integrated circuit substrate is disclosed herein. The processing unit is designed to operate in accordance with a predefined sequence of program instructions stored within an instruction register. A memory, capable of storing information provided by the processing unit and occupying a larger area of the integrated circuit substrate than the processing unit, is also provided within the microprocessor integrated circuit. The memory may be implemented using, for example dynamic or static random-access memory. A variable output frequency system clock, such as generated by a ring oscillator, is also disposed on the integrated circuit substrate.

High performance microprocessor having variable speed system clock

A high performance, low cost microprocessor system having a variable speed system clock is disclosed herein. The microprocessor system includes an integrated circuit having a central processing unit and a ring oscillator variable speed system clock for clocking the microprocessor. The central processing unit and ring oscillator variable speed system clock each include a plurality of electronic devices of like type, which allows the central processing unit to operate at a variable processing frequency dependent upon a variable speed of the ring oscillator variable speed system clock. The microprocessor system may also include an input/output interface connected to exchange coupling control signals, address and data with the central processing unit. The input/output interface is independently clocked by a second clock connected thereto.

A high-performance microprocessor system using instruction that access operands and instructions located relative to the current instruction group rather than located relative to the current instructions, as is the convention, is disclosed herein. The microprocessor system includes a central processing unit, memory, and a bus connecting the central processing unit and memory. An instruction fetching unit, connected to the bus, is provided for fetching instruction groups from the memory for use by the central processing unit and for storage within an instruction register. An instruction supplying unit operates to supply, in succession from the instruction register to the central processing unit, one or more instructions from each of the instruction groups. The system further includes an instruction decoder for configuring the instruction supplying unit to select, from the instruction register, operands associated with instructions from particular instruction groups.

High performance microprocessor using instructions that operate within

A microprocessor including a central processing unit connected to a push-down stack is disclosed herein. The push-down stack includes a first plurality of latches corresponding to a like first plurality of stack elements, and a second plurality of locations of random access memory corresponding to a like second plurality of stack elements. The first and second plurality of stack elements are provided in a single integrated circuit with the microprocessor. The push-down stack further includes a third plurality of memory locations in a system random access memory, with the third plurality of memory locations corresponding to a like third plurality of stack elements. In operation, up to a first plurality of items initially stored in the first plurality of stack elements are transferred therefrom without accessing the second plurality of stack elements. When the first plurality of stack elements are empty, up to a second plurality of items may be transferred thereto from the second plurality of stack elements. Similarly, up to the second plurality of items may be transferred from the second plurality of stack elements without accessing the third plurality of stack elements. In addition, up to a third plurality of items may be transferred from the third plurality of stack elements to the second plurality of stack elements when the second plurality of stack elements become empty.

Microprocessor system with hierarchical stack and method of operation

A data processing system in which timing of data transfer operations are adjusted in response to bus load variation is disclosed herein. The data processing system includes a microprocessor having a sensing circuit, and a driver circuit disposed to impress a signal upon a control line. The control line is also connected to the sensing circuit, as well as to one or more devices external to the microprocessor. The sensing circuit is configured to monitor a response time required for the signal impressed upon the control line to reach a predetermined electrical level, wherein the response time is a function of the number of devices coupled to the control line. The microprocessor is disposed to adjust the timing of data transfer between the microprocessor and the one or more devices external to the microprocessor based upon the monitored response time.

Data processing system having load dependent bus timing

A microprocessor (50) includes a main central processing unit (CPU) (70) and a separate direct memory access (DMA) CPU (72) in a single integrated circuit making up the microprocessor (50). The main CPU (70) has a first 16 deep push down stack (74), which has a top item register (76) and a next item register (78), respectively connected to provide inputs to an arithmetic logic unit (ALU) (80) by lines (82) and (84). An output of the ALU (80) is connected to the top item register (76) by line (86). The output of the top item register at (82) is also connected by line (88) to an internal data bus (90). A loop counter (92) is connected to a decrementer (94) by lines (96) and (98). The loop counter (92) is bidirectionally connected to the internal data bus (90) by line (100). Stack pointer (102), return stack pointer ( 104), mode register (106) and instruction register (108) are also connected to the internal data bus (90) by lines (110), (112), (114) and (116), respectively. The internal data bus (90) is connected to memory controller (118) and to gate (120). The gate (120) provides inputs on lines (122), (124), and (126) to X register (128), program counter (130) and Y register (132) of return push down stack (134). The X register (128), program counter (130) and Y register (132) provide outputs to internal address bus (136) on lines (138), (140) and (142). The internal address bus provides inputs to the memory controller (118) and to an incrementer (144). The incrementer (144) provides inputs to the X register, program counter and Y register via lines (146), (122), (124) and (126). The DMA CPU (72) provides inputs to the memory controller (118) on line (148). The memory controller (118) is connected to a RAM by address/data bus (150) and control lines (152).

High performance, low cost microprocessor

A microprocessor (50) includes a main central processing unit (CPU) (70) and a separate direct memory access (DMA) CPU (72) in a single integrated circuit making up the microprocessor (50). The main CPU (70) has a first 16 deep push down tack (74), which has a to item register (76) and a next item register (78), respectively connected to provide inputs to an arithmetic logic unit (ALU) (80) by lines (82) and (84). An output of the ALU (80) is connected to the top item register at (82) is also connected by line (88) to an internal data bus (90). CPU (70) is pipeline free. The simplified CPU (70) requires fewer transistors to implement than pipelined architectures, yet produces performance which matches or exceeds existing techniques. The DMA CPU (72) provides inputs to the memory controller (118) on line (148). The memory controller (118) is connected to a RAM by address/data bus (150) and control lines (152). The DMA CPU (72) enables the CPU (70) to execute instructions four times faster than the RAM speed by fetching four instructions in a single memory cycle.

Growing community of inventors

Dallas, TX, United States of America

Russell H Fish, Iii