Rca Inc.

Russell G Ott

Joel Roy Oberman

Robert A Dwyer

In a data processor system, a method for transferring data to and from a random access memory (RAM) with a serial data interface and having accessible word location includes the steps of generating a timing pulse consisting of contiguous time slots each defined by the Nth count of a counter, generating an initial address signal in the first occurring contiguous time slot of the timing pulse with the initial address signal including a read/write command signal, incrementing the initial address signal at each Nth count of the counter to form data address signal, accessing memory locations in the RAM with the initial address signal followed by said data address signals, supplying data words to or reading data words from the RAM at the word locations accessed by the data address signals in response to each Nth count of the counter and when the data address signal contains a write command or a read command signal, respectively.

Multiple byte serial data transfer protocol

A timing system which includes a timer circuit, a source of first clock pulses for advancing the timer circuit, and a circuit for reading out the timer circuit in synchronism advanced therewith and where there is also included a second source of clock pulses asynchronous with respect to the first source of clock pulses, a synchronizing circuit is provided for storing an indication of the receipt of each second clock source pulse. Then the timer is advanced only when a pulse is produced by the first clock source and the indication is present that a signal has been produced by the second clock source.

Clock synchronization circuit for a computer timer

A universal interface adaptor circuit (UIAC) for connecting any one of a plurality of either of two general microprocessor types to a peripheral device using the same interface connections to selectively generate and supply either a WRITE ENABLE signal or a READ ENABLE signal to a peripheral device. A first of the two general types of microprocessors is used in multiplexed-bus multiprocessor (MBM) systems and the second of the two general types of microprocessors is used in non-multiplexed-bus microprocessor (NMBM) systems, where the microprocessors used in both the MBM and the NMBM systems each supply three output signals for determining whether the function is a READ or a WRITE function and the time of occurrence of such READ or WRITE function. The UIAC comprises logic array having three input terminals X, Y, and Z for receiving the three output signals from each of the microprocessors employed in either the MBM systems or the NMBM systems. First selected logic elements of the logic array respond to the three output signals received from the MBM type systems to produce a READ ENABLE signal when the signals thereon indicate a READ function and a WRITE ENABLE signal when the signals thereon indicate a WRITE function, and second selected logic elements of the logic array respond to the three output signals received from the NMBM type systems to produce a READ ENABLE signal when the signals thereon indicate a READ function, and to produce a WRITE ENABLE signal when the signals thereon indicate a WRITE function.

Universal interface circuit for microprocessor peripherals

In a system having N devices all using a common data bus (CDB), a priority resolution circuit (PRC) for determining that particular device of the N devices which shall obtain control of the CDB when a device other than the particular device is attempting to obtain control of the CDB and comprising first logic common to all of the devices. A first control bus is common to every device and has a high signal level (SL) thereon when none of the devices is attempting to obtain control of the common data bus and a low SL thereon when any of the devices is attempting to obtain control of the CDB; and a second control bus is common to every device and has a low SL thereon when none of the devices has control of the CDB and a high SL thereon when any of the devices has control of the CDB. Each of the devices, including the particular device, comprises second logic for testing the SL on the first common control bus and responsive to the high SL on the first common control bus to then test the SL on the second common control bus. The second logic of the particular device is further responsive to the low SL of second common control bus to obtain control of the CDB.

Priority arbitration logic for a multi-master bus system

An oscillator circuit operable in different modes. The oscillator circuit, when operated as a crystal oscillator, is initially operated as a standard inverter oscillator requiring a low start-up voltage. Once the circuit oscillates, an hysteresis feedback network is inserted in the amplifying section of the oscillator providing a clock signal with sharper leading and falling edges. The circuit thus enables the start up of the oscillator at low voltages and ensures greater noise immunity following start-up. The oscillator circuit, when operated as an RC oscillator, may be operated as a Schmitt-trigger oscillator as soon as the oscillator is turned-on.

Switchable oscillator circuit

In a data processing system having a memory and employing N-bit bytes and two byte addresses, a branch instruction which can cross one page boundary is executed without having to use calculations to effect a change in the contents of the program counter (PC). It is determined whether the value V1 of the (N-1) least significant bits (LSB's ) of the lower order byte of the two byte branch address is greater or less than the value V2 of the (N-1) least significant bits (LSB's) of the lower order byte of the address to which the PC is pointing and also whether PC N.noteq.BR N where PC N and BR N are the most significant bits of the lower order bytes of the PC address and the branch address, respectively. If V1&lt;V2, PC N=1, and PC N.noteq.BR N, the upper order byte of the PC address is incremented by 1 and if V1&gt;V2, PC N=0, and PC N.noteq.BR 7, the upper order byte of the PC address is decremented by 1.

Implementation of instruction for a branch which can cross one page

Circuitry responsive to an input clock (C-clock) whose duty cycle is unknown produces two clocks (A and B) in addition to the input clock. One (A-clock) of the two clocks is skewed to have a greater duty cycle than the C-clock and the other one (B-clock) of the two clocks is skewed to have a lower duty cycle than the C-clock. The two phases of each one of the A and B-clocks are compared and control signals are produced indicative of the values of the respective duty cycles and, by deduction, of the duty cycle of the C clock. The values of the control signals determine which one of the A, B, or C clocks is selected as the system clock.

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Cranford, NJ, United States of America

Russell G Ott