Cisco Technology, Inc.

Russell E Schroter

John William Marshall

Atri Indiresan

Kenneth H Potter

Herman Levenson

Iwan Kartawira

Felix Yuan

A versatile and efficient technique for classifying packets in an intermediate node. According to the technique, criteria and rules associated with the packet are applied to one or more classification stages containing content-addressable memories (CAMs). Each stage examines specific criteria associated with the packet, e.g., a packet field, and generates a rule and additional criteria. The additional rule and criteria are provided to the next classification stage. This process continues until a final rule is provided to a final classification stage. At the final classification stage, the final rule is used to generate an identifier, e.g., queue identifier (ID), associated with the classified packet.

Programmable packet classification system using an array of uniform content-addressable memories

An inter-chip communication (ICC) mechanism enables any processor in a pipelined arrayed processing engine to communicate directly with any other processor of the engine over a low-latency communication path. The ICC mechanism includes a unidirectional control plane path that is separate from a data plane path of the engine and that accommodates control information flow among the processors. The mechanism thus enables inter-processor communication without sending messages over the data plane communication path extending through processors of each pipeline.

Inter-chip processor control plane communication

A lock controller supports both blocking and non-blocking lock requests issued by processors of a processing engine when attempting to access a shared resource of an intermediate network device. The non-blocking lock controller capability provides a processor with the flexibility to obtain other shared resources if the originally requested resource is not available. The blocking capability of the lock controller guarantees that each processor will eventually obtain the requested resource. By supporting both blocking and non-blocking capabilities, the lock controller provides increased flexibility and performance to the processors of the processing engine.

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Cary, NC, United States of America

Russell E Schroter