Qualcomm Incorporated

Semtech Corporation

Russell Deans

Chad Everett Winemiller

Jon Boyette

Li Hsiang Sun

Zhi Zhu

Zhiqin Chen

Chia Heng Chang

Minhan Chen

Kenneth Arcudia

Karl Richard Volk

Thomas Joseph Karpus

Hadi Goudarzi

Burcin Serter Ergun

David Paul Keesor

Behnam Amelifard

Kevin Wayne Spears

Mark Wesley Vilas

Paul Edward Hinson

Dror Barash

Jyotheeswara Reddy V

An apparatus, including: a phase locked loop (PLL) configured to generate a spread spectrum clock (SSC) clock signal where the SSC clock signal swings between a first frequency and a third frequency based on an SSC enable signal being asserted, or a non-SSC clock signal where the non-SSC clock signal is substantially constant at a second frequency based on the SSC enable signal being deasserted; and a control circuit configured to effectuate a first configuration change of the PLL in response to the SSC enable signal becoming deasserted, the first configuration change reducing a time interval between the SSC enable signal becoming deasserted and the non-SSC clock signal settling to substantially the second frequency.

Phase locked loop with decreased recovery time from disabling spread spectrum clock

In certain aspects, an apparatus includes a multiplexer having a first input, a second input, a select input, and an output, wherein the first input is configured to receive a first reference clock signal, the second input is configured to receive a second reference clock signal, and the select input is configured to receive a select signal. The multiplexer is configured to select one of the first and second reference clock signals based on the select signal, and output the selected one of the first and second reference clock signals at the output of the multiplexer. The apparatus also includes a clock driver having an input and an output, wherein the input of the clock driver is coupled to the output of the multiplexer.

Efficient clock forwarding scheme

A receiver is provided that generates a data sampling clock that is offset by clock offset that is a function of a decision feedback equalizer gain to account for a data sampling timing error that would occur without the clock delay.

Receiver with cancellation of intrinsic offset from decision feedback equalization to enhance data margin

Power saving systems and methods for Universal Serial Bus (USB) systems are disclosed. When a USB physical layer (PHY) enters a U3 low power state, not only are normal elements powered down, but also circuitry within the USB PHY associated with detection of a low frequency periodic signal (LFPS) wake up signal is powered down. A low speed reference clock signal is still received by the USB PHY, and a medium speed clock within the USB PHY is activated once per period of the low speed reference clock signal. The medium speed clock activates the signal detection circuitry and samples a line for the LFPS. If no LFPS is detected, the signal detection circuitry and the medium speed clock return to low power until the next period of the low speed reference clock signal. If the LFPS is detected, the USB PHY returns to a U0 active power state.

Power saving systems and methods for Universal Serial Bus (USB) systems

Aspects disclosed in the detailed description include high-frequency signal observations in electronic systems. In this regard, a high-frequency signal observation circuit is provided in an electronic system to enable high-frequency signal observations. In one aspect, the high-frequency signal observation circuit comprises an observation signal selection circuit. The observation signal selection circuit is programmably controlled to select an observation signal among a plurality of electronic input signals (e.g., control signals) received from the electronic system. In another aspect, the high-frequency signal observation circuit is configured to utilize a bypass data path, which is routed around serializer/deserializer (SerDes) logic in the electronic system, to output the observation signal for observation. By programmably selecting the observation signal and outputting the observation signal via the bypass data path, it is possible to examine accurately any high-frequency signal (e.g., high-frequency clock signal) in the electronic system with minimized delay and/or degradation in the high-frequency signal.

High-frequency signal observations in electronic systems

Methods and systems for shared control of a phase locked loop (PLL) for a multi-port physical layer (PHY) are disclosed. In one aspect, an arbitration logic circuit is coupled to ports of a multi-port PHY sharing a phase locked loop (PLL). Upon receiving an indication that the shared PLL is to be reset, the arbitration logic circuit commands the ports sharing the PLL to enter a state in which any reset of the shared PLL would have minimal or no effect in their operations. In this manner, an integrated circuit (IC) including a multi-port PHY may be configured with only one PLL and associated clock generating logic to provide a clock signal for some or all of its ports, thus reducing its semiconductor area and power consumption. Furthermore, the ports of the multi-port PHY may operate independently from each other obviating any configuration and/or interoperability problems associated with having a shared PLL.

Shared control of a phase locked loop (PLL) for a multi-port physical layer (PHY)

Aspects disclosed in the detailed description include apparatuses, methods, and systems for glitch-free clock switching. In this regard, in one aspect, an electronic circuit is switched from a lower-frequency reference clock to a higher-frequency reference clock. An oscillation detection logic is configured to determine the stability of the higher-frequency reference clock prior to switching the electronic circuit to the higher-frequency reference clock. The oscillation detection logic derives a sampled clock signal from the higher-frequency reference clock, wherein the sampled clock signal has a slower frequency than the lower-frequency reference clock. The oscillation detection logic then compares the sampled clock signal against the lower-frequency reference clock to determine the stability of the higher-frequency reference clock. By deterministically detecting stability of a reference clock prior to switching to the reference clock, it is possible to avoid premature switching to an unstable reference clock, thus providing glitch-free clock switching in the electronic circuit.

Apparatuses, methods, and systems for glitch-free clock switching

A system and method is provided for preventing a dropout of an LED current. In one embodiment of the present invention, the system includes a voltage source, a first circuit, a second circuit, a controller, and at least one LED. The first circuit receives a reference voltage from the voltage source, receives set-point current data from the controller, and uses the reference voltage and the set-point current data to produce a threshold voltage. The threshold voltage is then provided to the second circuit, where it is converted into an output current, which is drawn through the LED. The second circuit then compares the threshold voltage to an output voltage corresponding to the output current, and provides an output to the controller. The controller then uses the output to determine whether a dropout has occurred. If a dropout has occurred, then second set-point current data is provided to the first circuit.

Growing community of inventors

Chapel Hill, NC, United States of America

Russell Deans