Intel Corporation

Russell D Eslick

David M Brown

Kurt B Robinson

Brian L Dipert

Lily C Pao

Markus A Levy

Duane R Mills

David S Brannam

Michel I Ishac

Lawrence M Leszczynski

A powerdown controller receives a powerdown signal and causes a powerdown if the powerdown signal indicates a powerdown condition. An override signal also forces the powerdown controller to cause the powerdown when the powerdown signal is not indicating the powerdown condition. An override circuit generates the override signal if the powerdown condition is desired and the powerdown signal is not indicating the powerdown condition.

Override signal for forcing a powerdown of a flash memory

A memory card includes a plurality of memories, each having an array that includes a first block and a second block. Control circuitry is coupled to the array for controlling memory operations of the array. A block write protect circuit is provided for storing block lock data to selectively lock control circuitry from accessing the array for the memory operations. The block write protect circuit locks the control circuit from accessing (1) the first block when the block write protect circuit stores a first datum of the data and (2) the second block when the block write protect circuit stores a second datum of the data. A control input is coupled to the block write protect circuit for applying a control signal to enable the block write protect circuit to lock the control circuitry in accordance with the data. The memory card further includes a register circuit coupled to the control input of each of the plurality of memories for storing a control datum to generate the control signal. When the register circuit stores the control datum to generate the control signal, the block write protect circuit of each of the plurality of memories is enabled to lock the respective control circuitry from selectively accessing the respective first and second blocks in accordance with the respective block lock data.

Memory card with erasure blocks and circuitry for selectively protecting

A flash memory card is described. One flash memory card has circuitry for providing a ready output signal that indicates a first in time transition from a busy mode to a ready mode by either a first flash memory or a second flash memory of the flash memory card. One flash memory card has a power control register that is used to place certain flash memories in a power down mode. One flash memory card retains information in a power control register from a time prior to the entering of a global power down mode to a time after exiting of the global power down mode. One flash memory card has jumpers for indicating how many flash memories are present on the flash memory card.

Flash memory card with power control register and jumpers

A flash memory card is described. One flash memory card has addressable circuitry for selectively causing first, second, and third flash memories to operate in an active mode concurrently.

Flash memory card with all zones chip enable circuitry

A flash memory card is described which has a plurality of flash memories, each having a ready/busy output for indicating whether its respective one of the plurality of flash memories is busy or ready. A register circuit is provided for storing a plurality of mask data. A mode circuit is provided for choosing one of a first mode and a second mode, wherein a first mode signal is produced if the first mode is chosen and a second mode signal is produced if the second mode is chosen. A logic circuit is provided for performing logical operations with respect to the ready/busy output for each of the plurality of flash memories and the mask data in accordance with whether the first mode signal or the second mode signal is produced. If the first mode is chosen, the logic circuit produces a ready signal output for the flash memory card only if the ready/busy output of all the plurality of flash memories is ready. If the second mode is chosen, the logic circuit produces a ready signal output for the flash memory card each time any flash memory goes from being busy to being ready.

Flash memory card including plural flash memories and circuitry for

A flash memory card is described which includes a first flash memory and a second flash memory. The first flash memory includes an unmasked first output that enters a first state if the first flash memory is ready and a second state if the first flash memory is busy. The second flash memory includes an unmasked second output that enters the first state if the second flash memory is ready and the second state if the second flash memory is busy. The flash memory card also includes a circuit for selectively providing one of (1) a masked first output (2) the unmasked first output, (3) a masked second output, and (4) the unmasked second output. A latch provides a first ready output signal for the flash memory card. The first ready output signal indicates a first transition from the second state to the first state by one of the unmasked first output of the first flash memory and the unmasked second output of the second flash memory. A circuit is also provided for clearing the first ready output signal from the latch.

Flash memory card including circuitry for selectively providing masked

A flash memory card is described which has a ready/busy mask register. First and second flash memories of the flash memory card have respective first and second outputs indicating ready or busy status for the first and second memories. The ready/busy mask register contains mask data. Logic circuitry performs (1) a first logical operation between a first output and a first mask datum to produce a first masked output, (2) a second logical operation between a second output and a second mask datum to produce a second masked output, and (3) a third logical operation between the first masked output and the second masked output to produce a flash memory card ready/busy output. The flash memory card has circuitry for providing a ready output signal that indicates a first (in time) transition from a busy mode to a ready mode by either the first flash memory or the second flash memory of the flash memory card.

Flash memory card with a ready/busy mask register

A nonvolatile memory card includes a power supply input for receiving a device power supply voltage for the memory card and a plurality of memories arranged in an array. Each of the plurality of memories receives the device power supply voltage from the power supply input. Each of the plurality of memories receives a device power supply voltage indication signal that indicates voltage level of the device power supply voltage and configures circuitry within each of the plurality of memories to operate in accordance with the voltage level of the device power supply voltage. A voltage detection circuit is coupled to the power supply input for detecting the voltage level of the device power supply voltage and for generating the device power supply voltage indication signal. A logic is coupled to the voltage detection circuit and each of the plurality of memories for (1) receiving the device power supply voltage indication signal from the voltage detection circuit, (2) applying the device power supply voltage indication signal to each of the plurality of memories such that the circuitry of each of the plurality of memories is configured in accordance with the device power supply voltage indication signal, and (3) supplying data of the nonvolatile memory card with respect to the voltage level of the device power supply voltage to external circuitry.

Growing community of inventors

Placerville, CA, United States of America

Russell D Eslick