Silicon Laboratories Inc.

Cirrus Logic Inc.

Skyworks Solutions, Inc.

Nxp B.v.

St-ericsson Sa

Russell Croman

Dan Bernard Kasha

Michael Johnson

Michael R May

Scott Willingham

Scott Thomas Haban

Younes Djadi

Donald A Kerth

Marius Goldenberg

Javier Elenes

Jing Li

Aslamali A Rafi

G Diwakar Vishakhadatta

Augusto Manuel Marques

Srisai Rao Seethamraju

Stefan N Mastovich

Thomas C Fowler

Nebojsa Stanic

Mike R May

Jeffrey William Scott

John M Khoury

Richard T Behrens

G Tyson Tuttle

Jerrell P Hein

Vishnu Shankar Srinivasan

Aaron J Caffee

Peter Vancorenland

George Tyson Tuttle

Brian G Drost

Lionel Cimaz

Dylan Alexander Hester

Brian Douglas Green

James David Barnette

Lysander Lim

Ramkishore Ganti

Russell Alvin Schultz

Navin Harwalkar

Mark May

James P Maligeorgos

Thomas Glen Ragan

Carl Alelyunas

Xiaochuan Guo

Greg Hodgson

Wade Robert Gillham

Matthew M Kostelnik

Christopher S Gregg

Nisha Ganwani

Jonathan D Pearce

Tim Stroud

Lokesh Duraiappah

Xiachuan Guo

Tarang Shah

Brian Green

An integrated circuit has an isolation capacitor structure that reduces the risk of breakdown from high electric fields at the edge of the top metal plate of the capacitor. The capacitor structure includes a bottom metal plate above a substrate. A first dielectric layer of a first dielectric material is formed between the bottom metal plate and the top metal plate. The capacitor structure also includes a thin narrow ring formed of a second dielectric material located under a portion of the top metal plate. The second dielectric material has a higher dielectric constant than the first dielectric material. The thin narrow ring follows the shape of the edge of the top metal plate with a portion of the ring underneath the top metal plate and a portion outside the edge of the top metal plate to thereby be located at a place of the maximum electric field.

High dielectric constant material at locations of high fields

A fractional-N phase-locked loop (PLL) has a time-to-voltage converter with second order non linearity. The time-to voltage-converter provides an analog error signal indicating a phase difference between the reference clock signal with a period error and a feedback signal supplied by a fractional-N feedback divider. The spur results in quantization noise associated with the fractional-N feedback divider being frequency translated. To address the frequency translated noise, a spur cancellation circuit receives a residue signal indicative of the quantization noise and a spur signal indicative of the spur. The non-linearity of the time-to-voltage converter is mimicked digitally through terms of a polynomial generated to cancel the noise. The generated polynomial is coupled to a delta sigma modulator that controls a digital to analog converter that adds/subtracts a voltage value to/from the error signal to thereby cancel the quantization noise including the frequency translated quantization noise.

Spur and quantization noise cancellation for PLLS with non-linear phase detection

A sine to square wave converter circuit receives a sine wave signal and supplies a first square wave signal having a first frequency. A 2&#xd7; clock multiplier circuit multiplies the first square wave signal and supplies a second square wave signal with a second frequency that is twice the first frequency. A first storage element that is clocked by the second square wave signal stores a delayed version of the first square wave signal and supplies an even-odd signal. A second storage element that is clocked by the second square wave signal receives the even-odd signal and supplies an odd-even signal. A duty cycle correction circuit adjusts the threshold of the sine to square wave converter based on a difference in duty pulse widths between the even-odd signal and the odd-even signal.

Noise canceling technique for a sine to square wave converter

A clock generator includes an oscillator configured to generate an oscillating signal and a signal path configured to provide an output clock signal based on the oscillating signal. In response to a control signal, the clock generator is configured to neutralize periodic phase perturbations in the oscillating signal using opposing periodic phase perturbations. The neutralization may occur in the signal path. The signal path may be responsive to the control signal to adjust at least one of a duty cycle, a rise time, and a fall time of the output clock signal to cause alternating phase perturbations of the periodic phase perturbations to apply as the opposing periodic phase perturbations in the output clock signal. The neutralization may occur in the oscillator. The clock generator may include an auxiliary path configured to provide an auxiliary signal to the oscillator.

Neutralization of phase perturbations from deterministic electromagnetic interference

In one embodiment, a noise cancellation circuit includes: a window generator to generate a window having a first set of samples; a band splitter to split the window into pairs of symmetric frequency components; a processing circuit, for each of the pairs, to: compare a first magnitude of a first symmetric frequency component to a second magnitude of a second symmetric frequency component and modify one of the components based at least in part on the comparison; an integrator to integrate the pairs output from the processing circuit; and a second window generator to generate a second window having a second set of samples.

Performing noise cancellation in radio signals using spectral duplication

In an example, a method includes: in a first mode, causing a first tuner of an entertainment system to receive and process a first RF signal from a first antenna configured for a first band to output a first audio signal of a first radio station and causing a second tuner of the entertainment system to receive a second RF signal from a second antenna configured for the first band to determine signal quality metrics for one or more radio stations of the first band; in a second mode, causing the first tuner to output a first signal representation of the first RF signal and causing the second tuner to receive and process the second RF signal to output a second signal representation of the second RF signal; and causing a phase diversity combining circuit to process the first and second signal representations to output an audio signal of the first radio station, without disruption of output from the entertainment system of a broadcast of the first radio station.

Fully flexible multi-tuner front end architecture for a receiver

Circuitry and methods are disclosed that may employ common mode calibration circuitry configured to at least partially calibrate out impedance differences or mismatches between the differential signal paths of differential signal circuitry. The common mode calibration circuitry may be integrated as an internal part of integrated differential signal circuitry that includes a differential amplifier to reject common mode noise, and may be used to reduce or substantially eliminate any external and/or internal difference in signal path resistance that exists between the differential signal paths of the integrated differential signal circuitry. A common mode calibration signal may be internally or externally applied to the signal inputs of differential signal circuitry, and used to determine a setting for the common mode calibration circuitry that at least partially calibrates out impedance differences or mismatches between the differential signal paths of differential signal circuitry.

Circuitry and methods for common-mode rejection calibration

Embodiments include circuit devices and methods for re-clocking an input signal. In an embodiment, a circuit device includes a data storage element having a data input to receive a digital data stream having a first clock rate and including a clock input to receive a clock signal having a second clock rate. The data storage element further includes logic to adjust edge timing of transitions within the digital data stream based on the clock signal to produce a modulated output signal having a power spectrum with spectral nulls at a desired frequency and its harmonics without changing an average data rate.

Circuit devices and methods for re-clocking an input signal

A long-wave or medium-wave receiver receives a first signal from a first terminal of a loopstick antenna on a positive antenna input terminal of the receiver and receives a second signal from a second terminal of the loopstick antenna on a negative antenna input terminal of the receiver. The first and second signals are processed differentially in the receiver. The receiver may optionally be configured to operate in either a differential mode or a single-ended mode by setting switches to selectively connect one of the antenna input terminals to ground in single-ended mode.

Differential loopstick antenna configuration

A radio receiver and method of operating the same are disclosed. In one embodiment, the radio receiver may include a RF receive path configured to convey a first radio signal within a first band to a radio tuning circuit. The RF receive path may be controllable using a first AGC circuit. The radio receiver may also include a loop-through path configured to convey a second radio signal within a second band between an input and an output of the radio receiver. The second band may be different from the first band. The loop-through path may be controllable using a second AGC circuit.

Receiver chip with multiple independent loop-through paths

Systems and methods are disclosed that implement multiple inter-chip (IC) links to communicate digital signals and data between multiple tuner circuit chips of a radio frequency (RF) antenna diversity system. The multiple IC communication links may be employed, for example, to simultaneously communicate different signals and/or data between individual tuner circuit chips of a multi-signal type antenna diversity system in an asynchronous manner, and may be employed to achieve simultaneous antenna diversity for multiple RF signal types using a scalable IC communication link architecture that includes multiple IC communication links to interconnect a varying number of RF tuner circuit chips.

Systems and methods using multiple inter-chip (IC) links for antenna diversity and/or debug

In one embodiment, the present invention includes a method for configuring a single chip radio tuner having a configurable front end, which may be adapted within an integrated circuit (IC). The method may include setting a controller of the tuner with configuration information for a radio in which the tuner is located. Then, control signals responsive to the configuration information can be sent to the configurable front end to configure the tuner.

Integrating components in a radio tuner integrated circuit (IC) for a tracking filter

A tuner circuit includes circuitry to produce a first DSP frame based on a first RF signal and includes an inter-chip receiver circuit coupled to an inter-chip link and configured to receive an inter-chip frame. The inter-chip receiver circuit is configured to detect a start of frame symbol of the inter-chip frame and to extract a DSP offset and data related to a second DSP frame from the inter-chip frame. The tuner circuit further includes a digital signal processor coupled to the circuitry and to the inter-chip receiver circuit. The digital signal processor synchronizes the first DSP frame with the second DSP frame based on the start of frame symbol and the digital signal processor offset. The digital signal processor performs a selected antenna diversity operation on the first and second DSP frames to produce an output signal.

Antenna diversity system with frame synchronization

Growing community of inventors

Austin, TX, United States of America

Russell Croman