International Business Machines Corporation

Other

Russell C Lange

Martin Revitz

Bernard S Meyerson

Karen A Nummy

Robert Rosenberg

Wen-Yuan Wang

Jeffrey L Blouse

Inge G Fulton

Roy E Scheuerlein

Seshadri Subbanna

Paul J Tsang

Manu J Tejwani

Paul Andrew Ronsheim

David C Ahlgren

Ronald W Knepper

Shao-Fu S Chu

San-Mei Ku

Robert K Cook

Bob H Yun

Robert E Bendernagel

Subodh K Kulkarni

Cheryl B Field

Joseph F Shephard

A method of controlling the interfacial oxygen concentration of a monocrystalline/polycrystalline emitter includes the steps of: passivating the monocrystalline silicon surface by immersing the wafer in a diluted HF acid solution; transferring the wafer into a high vacuum environment; heating the wafer to between 400.degree. and 700.degree. C.; exposing the monocrystalline silicon surface to a gas having a partial pressure of oxygen of between 10.sup.-5 to 1 Torr for between 1 and 100 minutes; and, depositing polysilicon onto the monocrystalline silicon surface.

Method for controlling interfacial oxide at a

There is provided a method for use in the fabrication of a transistor, the method including the steps of: providing a substrate of semiconductor material including a region of first conductivity type; forming a first layer of second conductivity type epitaxial semiconductor material over the region; forming a second layer of second conductivity type epitaxial semiconductor material over the first layer, the second layer of a relatively higher dopant concentration than the first layer; oxidizing a portion of the second layer; and removing the oxidized portion of the second layer to expose a portion of the first layer, the exposed portion of the first layer forming an intrinsic base region. The steps of forming the first and second layers are preferably performed using low temperature, ultra-high vacuum, epitaxial deposition processes.

Narrow base transistor and method of fabricating same

A method of forming a semiconductor device on a body of semiconductor material having a first doped region of a first conductivity type, comprising the steps of: forming a stud over the first doped region; using the stud as a mask to form a second doped region of a second conductivity type in the surface of the first doped region adjoining the stud; forming a sidewall of insulating material on the stud; forming a first device contact within the sidewall; and forming a second device contact over the second doped region adjoining the sidewall, such that the first and second electrical contacts are separated by the sidewall. In accordance with an embodiment of the present invention, the step of forming the second device contact includes the steps of forming a layer of conductive material generally conformally over the first doped region and the stud, and then planarizing the layer of conductive material to a height equal to or less than that of the sidewalls. The second contact is thus self-aligned with the first and second doped regions and the first device contact. The method of the present invention can be utilized to fabricate bipolar transistors, insulated gate transistors, and BICMOS logic including both types of transistors. It can further be used to fabricate any other type of semiconductor device which utilizes the self-aligned, closely spaced device regions and contacts of the present invention.

Process of making BiCMOS devices having closely spaced device regions

Method of fabricating a narrow base transistor

A method for fabricating a bipolar transistor having a base doping variation of less than 20% is disclosed. A polysilicon base contact bipolar transistor is formed up to the point just prior to the intrinsic base-emitter formation. The intrinsic base-emitter opening is then reactive ion etched through the polysilicon base contact layer down to and into a single crystal silicon body thereunder, whereby the surface of the single crystal silicon is damaged. A silicon dioxide layer is then grown on the exposed and damaged single crystal silicon to convert the damaged silicon surface into a silicon dioxide layer. The silicon dioxide layer is removed by chemical etching to expose undamaged single crystal silicon. A screen silicon dioxide layer 50 to 500 .ANG..+-.10%, e.g., 180 .ANG., is then formed on the thus exposed undamaged single crystal silicon. The intrinsic base region is then formed by ion implantation through the screen silicon dioxide layer, the emitter region is formed within the intrinsic base region and electrical contact is made to the various elements of the bipolar transistor.

Method for fabricating a bipolar transistor

A semiconductor memory produced in a unipolar technology includes a cell which has a diffusion storage capacitor with one overlying terminal being merged with a bit/sense line, the other capacitor terminal is a diffused region and is coupled through a word transfer device to a word line injector charge source held at a fixed voltage. To provide an organized array of these cells, each bit line cell includes a shared word line charge source held at a fixed voltage and formed at the surface of a semiconductor substrate. A diffusion storage capacitor also is formed at the surface of the semiconductor and spaced apart from the shared charge source. Information is written into each bit line capacitor by applying a voltage of either of two different magnitudes, representing 1 and 0 bits of information, to the respective bit line while a word selection pulse produces an inversion layer at the surface of the substrate between each bit line capacitor and its shared word line fixed voltage charge source. At the termination of the word pulse, the fixed voltage remains stored at the capacitor node. The capacitors having the larger voltage applied to the bit line terminal of the capacitors store the greater amount of charge. This charge can then be detected by measuring the voltage of the floating bit sense line when a word pulse again connects the fixed voltage charge source with each of its respective capacitors.

High speed merged charge memory

A memory is provided which includes a semiconductor substrate having a diffusion region disposed therein, first, second, third and fourth storage capacitors, first, second, third and fourth switching or transfer devices for coupling the first, second, third and fourth storage capacitors, respectively, to the diffusion region, a common conductor connected to the diffusion region and means for selectively activating the switching devices. In a more specific aspect of this invention, a plurality of groups of the four storage capacitors are arranged so that each of these capacitors is selectively coupled to the common conductor. In another aspect of this invention, the storage capacitors of the plurality of groups are arranged in parallel rows with the common conductor arranged obliquely to the direction of the rows of storage capacitors.

High density one device memory cell arrays

A method for providing very narrow resolvable line widths on a semiconductor substrate surface involves initial overexposure of a positive working photoresist through a mask so as to not only expose the portions of the photoresist corresponding to the transparent areas of the mask but to also expose the outer periphery of the photoresist areas corresponding to the opaque areas of the mask. Through subsequent processing, the areas of the substrate surface corresponding to the originally unexposed areas of the photoresist are made available for use in semiconductor fabrication, such as areas to be oxidized to function as narrow electrical isolation areas.

Method for forming narrow images on semiconductor substrates

An improved one-device random access memory cell comprises a transistor and a capacitor, with one of the transistor's controlled electrodes being connected to one of the capacitor plates to form a storage node. The storage node is maintained at either a first or a second voltage level depending upon the binary state of the cell. The other capacitor plate is connected to a voltage level which is approximately midway between the first and second voltage levels so that the maximum voltage across the capacitor is reduced to one half the voltage of prior art cells wherein the other capacitor plate was grounded or maintained at the memory power supply voltage level. By halving the maximum voltage across the capacitor, the capacitor dielectric thickness may be halved to thereby double the capacitance per unit area without exceeding the capacitor dielectric breakdown field strength.

One-device random access memory cell having enhanced capacitance

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Wappingers Falls, NY, United States of America

Russell C Lange