Renesas Technology America, Inc.

Mitsubishi Semiconductor America, Inc.

Russell C Deans

Gregory T Brauns

Vincent Acierno

D Lee Newman, Jr

Kevin Traynor

Brian Worobey

Bartt H Richards

Disclosed is an electrostatic discharge device, typically referred to as a power clamping circuit, for minimizing the effects of an initial ESD event as well as providing protection against subsequent ESD events. The power clamp is left fully turned on during and after an ESD event. Subsequent ESD events are those ESD events occurring shortly after an initial ESD event. By using a blocking device such as a diode, the power clamping circuit is maintained in a strong 'on' state that fully discharges the initial ESD event and allows for a more rapid response to subsequent ESD events.

Electrostatic discharge device with variable on time

A current-mode D/A converter is described having variable output and offset control. According to an exemplary embodiment, a first D/A converter includes a number of first control inputs and an output capable of generating a first current proportional to a number of active first control inputs. A driver includes an input connected to the output of the first D/A converter, a number of second control inputs, and an output capable of generating a second current proportional to the first current based on a number of active second control inputs. A second D/A converter includes a number of third control inputs and an output capable of generating a third current proportional to a number of active third control inputs. Offset control circuitry includes an input connected to the output of the second D/A converter, an offset control input, and an output connected to the output of the driver. The offset control circuitry is capable of summing the second and third currents at the output of the driver when the control input is active.

Current-mode D/A converter having variable output and offset control

Micro ROM testing is provided using timing logic and clocks utilized in normal operation of the micro ROM. A PLA in the micro ROM has its output lines coupled to read amplifiers that receive values read from the PLA locations selected by address inputs. The read amplifiers latch the PLA values into timing generators to produce timing signals of various types supplied to a microcontroller associated with the micro ROM. A test signal is supplied to the timing generators to disconnect them from the outputs of the read amplifiers and to establish a scan chain composed of the timing generators connected in series. Non-overlapping clock signals supplied by a system clock of the microcontroller cause the latched PLA values to shift through the timing generators in the scan chain. At a scan output of the last timing generator in the scan chain, the PLA values are observed and compared with the values expected from the selected PLA locations.

Micro ROM testing system using micro ROM timing circuitry for testing

Growing community of inventors

Durham, NC, United States of America

Russell C Deans