Hewlett-packard Company

Hewlett-packard Development Company, L.p.

Russell C Brockmann

Kevin Safford

Patrick Knebel

Gregory L Ranson

William S Jaffe

Leith L Johnson

Stephen R Undy

Karl P Brummel

Gregg Bernard Lesartre

Douglas Benson Hunt

Anuj Dua

Donald Charles Soltis, Jr

Barry Joseph Arnold

Steven T Mangelsdorf

James Earl McCormick, Jr

Joel D Lamb

Jeremy Petsinger

Robert E Naas

James Curtis Stout

Susith Rohana Fernando

David Carl Kubicek

Bruce A Long

William R Bryg

Rohit Bhatia

Jonathan P Lotz

John William Bockhaus

Chris Poirier

Paul L Perez

Duncan C Weir

Kevin Liao

Jane Wang

M A Susith Rohana Fernando

Brian M Kelly

A method of, and apparatus for, interfacing the hardware of a processor capable of processing instructions from more than one type of instruction set. More particularly, an engine responsible for fetching native instructions from a memory subsystem (such as an EM fetch engine) is interfaced with an engine that processes emulated instructions (such as an x86 engine). This is achieved using a handshake protocol, whereby the x86 engine sends an explicit fetch request signal to the EM fetch engine along with a fetch address. The EM fetch engine then accesses the memory subsystem and retrieves a line of instructions for subsequent decode and execution. The EM fetch engine sends this line of instructions to the x86 engine along with an explicit fetch complete signal. The EM fetch engine also includes a fetch address queue capable of holding the fetch addresses before they are processed by the EM fetch engine. The fetch requests are processed such that more than one fetch request may be pending at the same time. If a pending fetch request is canceled due to a pipeline flush, then the fetch address queue is cleared and the pending fetch requests are canceled. The system also prevents macroinstruction (MIQ)-related stalls by using a speculative write pointer to control the issuance of fetch requests, thereby preventing the MIQ from becoming oversubscribed.

Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine

The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles those microinstructions using a bundler, within an emulation engine. The bundles are issued in parallel and dispatched to the execution engine and contain pre-decode bits so that the execution engine treats them as microinstructions. Before being transferred to the execution engine, the instructions may be held in a buffer. The method also selects between bundled microinstructions from the emulation engine and native microinstructions coming directly from the fetch engine, by using a multiplexer or other means. Both native microinstructions and bundled microinstructions may be held in the buffer. The method also sends additional information to the execution engine.

Method and apparatus for implementing two architectures in a chip

An apparatus verifies the correctness of a behavioral model of a microcode machine, where the microcode machine is operable in a native state and an emulated state. The apparatus includes means for producing the native state, means for producing the emulated state, and means for comparing the native state and the emulated state. Corresponding to the apparatus, a method verifies the correctness of a processor behavioral model, where the processor operates in a native mode state and an emulated mode state. The method includes determining if a macroinstruction to be executed is a native instruction, and, if the macroinstruction is a native instruction, executing the native instruction, the execution producing the native mode state of the processor. The method further includes, if the macroinstruction is not a native instruction, fetching the macroinstruction, providing microinstructions corresponding to the macroinstruction, and executing the microinstructions, the execution producing the native mode state of the processor. Finally, the method includes executing the macroinstruction, the execution producing an emulated state of the processor, and comparing the native mode state the of the processor with the emulated state of the processor.

Method and apparatus for verifying the correctness of a processor behavioral model

A method and apparatus are provided for improving the rate at which macroinstructions are transformed into corresponding microinstructions. Encoding is added to a microcode storage device. The encoding indicates that a microinstruction flow will end in a determined number of cycles. The number of cycles is determined by the number of canceled instructions in a processing pipeline that would be introduced if no flow length prediction was used. For flow lengths less than a determined number of cycles, a hint bit is used in an entry point structure. For flow lengths greater than a determined length, a hint bit is encoded at a third line from an end of the microinstruction flow. Using this method, flows of any length can be hinted. Furthermore, flows that do not originate from the entry point structure can also be hinted. The method reduces the number of hint bits that are needed in the entry point structure and provides for better prediction.

Method and apparatus to reduce penalty of microcode lookup

A method and apparatus that utilizes a simple test and flush mechanism to implement branch instructions of one Instruction Set Architecture (ISA) using instructions of another ISA is described. During the decoding and sequencing of microinstructions to implement a branch instruction, a fix-up address, which represents the remedial branch target in the event of a mispredicted target or branch condition, is determined and stored. A test condition is set to determine if the prediction or the branch condition was correct. When the test condition fails, the instruction execution pipeline is immediately flushed to avoid executing any instruction remaining in the pipeline following the branch instructions. The flushing of the pipeline signals the instruction fetch control mechanism to redirect the instruction flow to the instruction corresponding to the fix-up address. A method and apparatus according to the present invention further allows flushing of the pipeline when conditions other than ones involved in branch instructions occurs, e.g., to flush stale instructions.

Apparatus and method for conditionally flushing a pipeline upon a failure of a test condition

An address space of a random access memory (&ldquo;RAM&rdquo;) is overlaid over an address space of a read-only memory (&ldquo;ROM&rdquo;) minimizing traditional address bits and loading of an address decoder. Word lines in the ROM in the overlap region are constructed without programming FETs. When the overlap region is addressed, the ROM is unable to change a pre-charged level of the ROM because of the lack of programming FETs. The RAM, however, is free to either leave the pre-charged level unchanged or to drive a node, as required. Thus, conflicts between the ROM and the RAM in the overlap region are eliminated and additional address bit are saved, and loading of address decoders is minimized.

Method and apparatus to minimize additional address bits and loading when adding a small patch RAM to a microcode ROM

An apparatus and a method of testing computer microarchitectures has a test writer create a test sequence written directly in microinstructions (both native-mode and emulation-only microinstructions). The microinstruction sequence is then inserted into a reprogrammable microcode storage, replacing the normal sequence of microinstructions for a given macroinstruction. In order to execute the microinstructions, the test writer can issue the macroinstruction. The method may be implemented in a simulation model where one set of microinstructions in the reprogrammable microcode storage can be easily replaced. The method may also be applied to an actual microprocessor implementation.

Method and apparatus for testing microarchitectural features by using tests written in microcode

A method and an apparatus checks the fine-grain correctness of a microcode machine central processor unit (CPU) behavioral model. Macroinstructions are decomposed into microinstructions and each microinstruction is executed sequentially. A sequence of microinstructions is determined by an emulated microinstruction sequencer, using dynamic execution information, including information from execution of prior microinstructions in the sequence of microinstructions. At the end of execution of each microinstruction, a reference state is compared to a corresponding state of the behavioral model, and any differences are noted. After execution of all microinstructions in the microinstruction sequence, a reference state is compared to a corresponding state of the behavioral model, and any differences are noted.

Method and apparatus for verifying the fine-grained correctness of a behavioral model of a central processor unit

A branch target structure predicts a branch target address for an instruction flow. To conserve space, only a portion of the branch target address is stored. The branch target address is reconstructed assuming that an unspecified portion of a current branch instruction address matches corresponding bits of the branch target address. A comparator determines if the unspecified portion of the current branch instruction address matches corresponding bits of the branch target address. If the unspecified portion of the current branch instruction address does not match the corresponding bits of the branch target address, update of the branch target structure is inhibited. Otherwise update allowed.

Method and apparatus for reducing branch prediction table pollution

The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles those microinstructions using a bundler, within an emulation engine. The bundles are issued in parallel and dispatched to the execution engine and contain pre-decode bits so that the execution engine treats them as microinstructions. Before being transferred to the execution engine, the instructions may be held in a buffer. The method also selects between bundled microinstructions from the emulation engine and native microinstructions coming directly from the fetch engine, by using a multiplexor or other means. Both native microinstructions and bundled microinstructions may be held in the buffer. The method also sends additional information to the execution engine.

Method and apparatus for implementing two architectures in a chip using bundles that contain microinstructions and template information

A method and an apparatus for re-creating a trace of instructions from an emulated instruction set when running on hardware optimized for a different instruction set, such as IA-32 instructions running on an IA-64 machine, are disclosed. An execution trace buffer is created that maintains desired information about instructions as they are executed and retired. The invention may be configured such that certain desired information helpful to debugging the system may be written to the buffer as the instructions are retired. This information may include the addresses of sequential or branch instructions, or other relevant information that can be gathered continuously and non-intrusively as instructions are executed. The information may be read from the buffer and output in a machine-visible form at the user's convenience.

Method and apparatus for re-creating the trace of an emulated instruction set when executed on hardware native to a different instruction set field

Method for detecting when first and second signal patterns have occurred on a split-transaction bus having transaction identifying indicia: Signal patterns occurring on the bus are compared with a first stored signal pattern. If a match is detected, the transaction identifying indicia that were associated on the bus with the first signal pattern are stored, and a first detection signal is asserted and held asserted. Signal patterns on the bus are then compared with a second stored signal pattern, and transaction identifying indicia occurring on the bus are compared with the indicia previously stored. A match signal is asserted when the first detection signal is asserted and, simultaneously, matches are detected for both of the second signal pattern comparison and the transaction identifying indicia comparison. Circuitry for implementing the method: First comparison circuitry asserts a first detection signal when a first signal pattern is detected on the bus. First storage circuitry stores a record of the first detection signal having been asserted. Second storage circuitry stores the transaction identifying indicia present on the bus when the first signal pattern is detected. Second comparison circuitry compares the signal patterns on the bus with a stored signal pattern, and third comparison circuitry compares the transaction identifying indicia present on the bus with the indicia stored in the second storage circuitry. When the second and third comparison circuitries simultaneously indicate matches and the first storage circuitry indicates that the first signal pattern was previously detected, output generation circuitry asserts a match signal.

Circuitry and method for detecting signal patterns on a bus using

Method of processing information in a microprocessor. At a first time during the life cycle of an instruction, a first set of microprocessor self-monitoring information is generated. The first set of mnicroprocessor self-monitoring information is stored, information necessary to execute the instruction is stored, and the two are associated. At a second time during the life cycle of the instruction, a second set of microprocessor self-monitoring information may be generated. This is also stored and is associated with the information necessary to execute the instruction. If the instruction retires, the first and second information may be retrieved for use in microprocessor testing. The information may also be used as soon as it is generated, for example by communicating the information itself or indicators derived from it to a state machine configured to facilitate microprocessor testing. The invention may also include a method of processing information in a microprocessor to facilitate microprocessor testing operations, wherein system bus monitoring information is generated whenever system bus accesses occur. This information, or indicators derived from it, is communicated to a microprocessor testing state machine on-chip with the microprocessor. In yet other embodiments, the invention may include the steps of: generating microprocessor self-monitoring information at various times during the life cycle of an instruction; utilizing the microprocessor self-monitoring information both when it becomes available as well as later, after retirement of the associated instruction; generating system bus monitoring information whenever system bus accesses occur; and utilizing the system bus monitoring information when it becomes available.

Method for processing information in a microprocessor to facilitate

Method for efficiently and flexibly comparing a group of multi-bit binary fields with a multi-bit expected pattern to generate a set of final match results, one final match result for each binary field in the group. Sets of of bit-wise comparator results are generated, one set for each binary field, by comparing each binary field with the expected pattern. Then, sets of bit-wise mask results are generated for each binary field by bit-wise masking each set of bit-wise comparator results with a mask pattern. Then, a set of preliminary match results is generated. Each preliminary match result is equal to the logical AND of all bits making up the bit-wise mask result set for the corresponding binary field. Then, a set of secondary match results is generated by negating all of the preliminary match results if a negate indicator is asserted. Finally, a set of final match results is generated, one final match result for each binary field, by individually gating all of the secondary match results with a separate enable indicator for each binary field. The invention includes an M.times.N comparator matrix for accomplishing the just-described method. The invention also includes circuitry for comparing N binary fields with an expected pattern to generate N comparison results.

Growing community of inventors

Fort Collins, CO, United States of America

Russell C Brockmann