Zilog, Inc.

Other

Ixys Ch Gmbh

Ixys Intl Limited

Russell Brent Lloyd

Randal Quincy Thornley

Bruce L Troutman

Joshua J Nekl

David Alan Roberts

A memory is organized into blocks. In a bit-flipping operation, a memory block is read, the read bit data values are inverted, and the inverted data is written back to the memory block. Inverted memory blocks are tracked by setting a flag bit in the memory block, or by storing a pointer to a memory block. In a read operation, a memory block is read and, if the tracking method indicates the memory block is inverted, the read data values are reverted before being returned. In a write operation, a memory block is read and, if the tracking method indicates the memory block is inverted, the write data values are inverted before being written. Inversion of data values and tracking of inverted memory blocks may be performed by a specialized memory controller or by a processor executing secure memory code. Data remanence is thus prevented in the memory.

Bit-flipping memory controller to prevent SRAM data remanence

A delay-locked loop (DLL) involves a pulse generating circuit that generates first and second pulses from an input clock signal. The second pulse is generated one clock signal period later than the first pulse. The first pulse is supplied to the input of a delay line. An edge of a delayed version of the first pulse as output from the delay line is phase-aligned with respect to a corresponding edge of the undelayed second pulse such that the DLL locks. The sending of pulses through the delay line of the DLL rather than clock signals having more edges per unit time helps reduce DLL aliasing problems and reduces the amount of switching in the delay line, thereby reducing power. consumption. A compact segmented delay line construction allows an input signal of arbitrary wave shape to be delayed by a fraction of the clock signal period.

Pulse matching delay-locked loop

This invention discloses a system to attach various photographic accessories to a camera by using an apparatus that attaches to the existing shoulder strap loop of a camera. The apparatus has a body, a strong hook to attach to the shoulder strap loop, and a thumbscrew that tightens the apparatus to the camera. The apparatus also incorporates an additional shoulder strap loop to replace the one covered when this system is used. Various mounting plates then attach to the body of the apparatus to which the various accessories are mounted.

Camera accessory mount using shoulder strap loop

A memory device includes memory cells that are overwritten in response to receipt of a clear request signal and an overwrite value. The clear request signal enables all word lines of the memory device to be overwritten. The clear request signal in combination with the overwrite value cause the overwrite value to be written to a first column of memory cells. At least two delay elements transfer the overwrite value to another column of memory cells after a delay. By use of at least two delay elements to delay and transfer the overwrite value to be written to another column of memory cells, a relatively low magnitude of current can be used to cause memory cells to be overwritten. In addition, the value and sequence of values that overwrite memory cells can be controlled.

Overwriting memory cells using low instantaneous current

The present invention provides a memory architecture allowing for instructions of variable length to be stored without wasted memory spaces. Instructions of one, two, and three bytes can all be retrieved in a single fetch. The exemplary embodiment divides the memory block into two &#xd7;16 memories having some special addressing circuitry. This structure logically arranges the memory into a number of rows, each of four byte-wide columns. To the first of these &#xd7;16 memories, the full address is provided. If the address is within the two columns of the second &#xd7;16 memory, the full address is also provided to the second &#xd7;16 memory. If the address is to the first of the &#xd7;16 memories, the second &#xd7;16 memory instead receives the portion of the address specifying the row with one added to it. This results in a dual row access with the last one or two bytes of 3-byte instruction being supplied by the row above the first byte. The net effect is that all the physical memory physical space is used for program code with none being wasted in the 24-bit access.

Architecture to relax memory performance requirements

The present invention provides a memory architecture allowing for instructions of variable length to be stored without wasted memory spaces. Instructions of one, two, and three bytes can all be retrieved in a single fetch. The exemplary embodiment divides the memory block into two &times;16 memories having some special addressing circuitry. This structure logically arranges the memory into a number of rows, each of four byte-wide columns. To the first of these &times;16 memories, the full address is provided. If the address is within the two columns of the second &times;16 memory, the full address is also provided to the second &times;16 memory. If the address is to the first of the &times;16 memories, the second &times;16 memory instead receives the portion of the address specifying the row with one added to it. This results in a dual row access with the last one or two bytes of 3-byte instruction being supplied by the row above the first byte. The net effect is that all the physical memory physical space is used for program code with none being wasted in the 24-bit access.

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Middleton, ID, United States of America

Russell Brent Lloyd