Lsi Logic Corporation

Russell B Stuber

Robert Wayne Moss

David O Sluiter

Christopher M Giles

Alan R Gilchrist

Randall S Miller

A data bus transfers data between at least one slave device and a plurality of master devices, and an arbiter grants access to each of the master devices. The slave device includes look-ahead apparatus that includes staging register for staging an identification of a master device and a decoder for comparing a staged identification to an identification of a command from the bus. The look-ahead apparatus issues split releases of a next master device while the slave device returns data associated with a prior command.

Look ahead split release for a data bus

A slave device on a data bus has a register that stores a non-queued split master vector containing bits identifying whether a transaction with corresponding master devices have been split. An input gate is responsive to the status of the slave device and to receipt of a command from a master device when the slave device status is busy to set a bit in the non-queued split master vector identifying that the transaction with the corresponding master device is split. An output gate is responsive to a not busy status of the slave device to output the non-queued split master vector to the arbiter to re-arbitrate use of the data bus among the previously-split non-queued master devices.

Apparatus for arbitrating non-queued split master devices on a data bus

When a master device resets, flush commands are issued to a flush master register in the slave devices. A comparator compares the identification of the master device associated with the flush command to an identification of the master device associated with data for return by the slave device. A gate is responsive to the comparator to flush data from the data register that are pending for return.

Apparatus for flushing slave transactions from resetting masters of a data bus

Ownership of a peripheral bus between a peripheral device and a plurality of master devices is assigned to one of the master devices. Each master device has an associated controller for controlling the peripheral device via the peripheral bus. Communication occurs without impediment between the master device and its controller that have ownership of the bus, thereby conducting transactions via the peripheral bus and peripheral device. Communication with the master device and controller not having ownership is blocked, making the controller look busy to the master device and making the master device look idle to the controller. The ownership is assigned to the master/controller pairs using an arbiter arrangement.

Process and apparatus for managing use of a peripheral bus among a plurality of controllers

A four-phase arbitration system employs a master and a slave arbiter. The master arbiter operates to provide ownership of a bus to a first device if a second device, coupled to the slave arbiter is not conducting a transaction. If the second device desires use of the bus, the slave arbiter sends a request to the master arbiter, which asserts an acknowledge signal for as long as the first device has ownership of the bus, and at least as long as a timeout of the first device. The master arbiter de-asserts its acknowledge signal when the first device ceases ownership of the bus. The slave arbiter is responsive to the de-assertion of the acknowledge signal to assert bus ownership to the second device. When the second device transaction is completed, its request signal is de-asserted to the master arbiter, causing the master arbiter to re-assert the acknowledge signal. Failure to receive a de-asserted acknowledge signal causes the slave arbiter to move to the next state.

Four-phase handshake arbitration

A slave device includes a command FIFO that stores commands for a device controller on a first-in, first-out basis to execute a read or write transaction. Commands are received from the data bus by an input register which supplies write commands to a dynamic stage register. A multiplexer couples the dynamic stage register and the input register to the command FIFO so that only the initial command of a single or multi-beat write burst is written to the command FIFO from the dynamic stage register. Consequently, separate write commands are not stored for each data beat, resulting in minimal areal size for the integrated circuit chip containing the command FIFO. Instead, a counter counts the number of beats in the multi-beat burst, so that when the last beat is received, the initial command and the beat count are supplied to the command FIFO. The device controller calculates the starting address of each subsequent data beat based on the prior beat address and the size of the data beat, to a limit established by the beat count. Non-queued read commands are transferred by the multiplexer directly from the input register to the command FIFO so that latency is not added to the processing of read commands.

Dynamic command buffer for a slave device on a data bus

Methods and associated structure for providing a substitute, predetermined, fixed length when transferring burst transactions from one device to another through a bridge device where the burst transaction has an indefinite length specified. In one exemplary preferred embodiment, an AMBA AHB bus bridge slave device recognizes initiation of burst transactions of a indefinite length and translates the indefinite length burst transactions on the first bus into appropriate bus transactions for application to a second bus or device having a predetermined fixed length for the transferred the burst transactions. In a second embodiment, a slave device acting as a bridge receives a burst of indefinite length and translates the bus request into one with a predetermined fixed length for application to a device controller. Preferably, the predetermined substitute burst length is configurable within the system to permit optimization of the predetermined fixed length in accordance with the needs of particular buses and devices within the system.

Methods and structure for transfer of burst transactions having unspecified length

A slave device receives commands from a master device for execution on a first-in, first-out basis. A status register is responsive to a queue of commands to provide a COMMAND_STATUS_FULL signal when the queue is full of commands. A configuration register provides a SHUT_DOWN signal identifying a shutdown status of the slave device. A bus control is responsive to the command and to either the COMMAND_STATUS_FULL or SHUT_DOWN signal to idle the data bus and deny the requesting master device access to the data bus if the command is for a non-locked transfer, or to stall the data bus if the command is for a locked transfer request.

Interface shutdown mode for a data bus slave

A slave device includes a queue that receives commands or data from a master device for execution on a first-in, first-out basis. A status register is responsive to the queue to provide a STATUS_FULL signal when the queue is full of commands and a STATUS_EMPTY signal when the queue is empty. A configuration register provides a DEBUG signal identifying a maintenance status of the slave device. A bus control provides a QUEUE_FULL signal in response to either (1) the STATUS_FULL signal or (2) the DEBUG signal and not the STATUS_EMPTY signal to split further commands or stall the data bus.

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Boulder, CO, United States of America

Russell B Stuber