Growing community of inventors

Sunnyvale, CA, United States of America

Russell B Segal

Average Co-Inventor Count = 1.56

ph-index = 8

The patent ph-index is calculated by counting the number of publications for which an author has been cited by other authors at least that same number of times.

Forward Citations = 206

Russell B SegalBrent L Gregory (8 patents)Russell B SegalBalkrishna R Rashingkar (3 patents)Russell B SegalPeiqing Zou (3 patents)Russell B SegalDouglas Chang (2 patents)Russell B SegalDavid L Peart (2 patents)Russell B SegalPaul Kingsley Rodman (1 patent)Russell B SegalYan Lin (1 patent)Russell B SegalKsenia Roze (1 patent)Russell B SegalMattias A Hembruch (1 patent)Russell B SegalAiguo Lu (1 patent)Russell B SegalRussell B Segal (22 patents)Brent L GregoryBrent L Gregory (15 patents)Balkrishna R RashingkarBalkrishna R Rashingkar (12 patents)Peiqing ZouPeiqing Zou (6 patents)Douglas ChangDouglas Chang (8 patents)David L PeartDavid L Peart (7 patents)Paul Kingsley RodmanPaul Kingsley Rodman (21 patents)Yan LinYan Lin (4 patents)Ksenia RozeKsenia Roze (3 patents)Mattias A HembruchMattias A Hembruch (1 patent)Aiguo LuAiguo Lu (1 patent)
..
Inventor’s number of patents
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Strength of working relationships

Company Filing History:

1. Synopsys, Inc. (21 from 2,493 patents)

2. Magam Design Automoation, Inc. (1 from 1 patent)


22 patents:

1. 9754070 - Path-based floorplan analysis

2. 9460258 - Shaping integrated with power network synthesis (PNS) for power grid (PG) alignment

3. 9390222 - Determining a set of timing paths for creating a circuit abstraction

4. 9189591 - Path-based floorplan analysis

5. 9026974 - Semiconductor integrated circuit partitioning and timing

6. 8914759 - Abstract creation

7. 8893073 - Displaying a congestion indicator for a channel in a circuit design layout

8. 7114142 - Optimizing locations of pins for blocks in a hierarchical physical design by using physical design information of a prior hierarchical physical design

9. 6678644 - Integrated circuit models having associated timing exception information therewith for use with electronic design automation

10. 6496972 - Method and system for circuit design top level and block optimization

11. 6438731 - Integrated circuit models having associated timing exception information therewith for use in circuit design optimizations

12. 6317863 - Method and apparatus for irregular datapath placement in a datapath placement tool

13. 6023568 - Extracting accurate and efficient timing models of latch-based designs

14. 5953235 - Method for processing a hardware independent user description to

15. 5790830 - Extracting accurate and efficient timing models of latch-based designs

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