Sigmatel, Inc.

Silicon Laboratories Inc.

Russell Alvin Schultz

Thomas A Zudock

Marc Kevin Jordan

Matthew Derrell Felder

Matthew Brady Henson

David Moore

Russell Croman

Dana John Taipale

Scott Thomas Haban

Younes Djadi

Jean Charles Pina

Alexander August Arthur Hakkola

Jean-Charles Pina

Jeffrey Patrick Gleason

A receiver includes a compressive factor generator configured to generate a compressive gain signal based on a digital demodulated received signal, a signal quality estimate, an upper modulation level, and a lower modulation level. The receiver includes a gain circuit configured to apply the compressive gain signal to the digital demodulated received signal. The compressive factor generator may include a peak tracking filter configured to generate a peak tracking signal based on the digital demodulated received signal and filter configuration information. The compressive factor generator may include a compression threshold generator configured to generate a modulation index based on the peak tracking signal, the signal quality estimate, the upper modulation level, and the lower modulation level. The compressive factor generator may include a compression curve and a gain compression hold and recovery processor.

Adaptive signal compressor for AM radio

Systems and methods are disclosed that implement multiple inter-chip (IC) links to communicate digital signals and data between multiple tuner circuit chips of a radio frequency (RF) antenna diversity system. The multiple IC communication links may be employed, for example, to simultaneously communicate different signals and/or data between individual tuner circuit chips of a multi-signal type antenna diversity system in an asynchronous manner, and may be employed to achieve simultaneous antenna diversity for multiple RF signal types using a scalable IC communication link architecture that includes multiple IC communication links to interconnect a varying number of RF tuner circuit chips.

Systems and methods using multiple inter-chip (IC) links for antenna diversity and/or debug

A method of charging a battery includes applying a charging current from a semiconductor device to the battery during a first battery charging time period. The method also includes measuring a charging voltage level at the battery during the first battery charging time period. During a non-charging voltage measurement time interval, the method includes temporarily stopping application of the charging current from the semiconductor device to the battery and measuring a non-charging voltage level at the battery while the charging current is not being applied to the battery.

Charging a secondary battery

A system and method for managing memory is disclosed. The system includes a computer memory array and a memory management unit accessible to the memory array. The memory management unit includes a plurality of parallel comparators. The comparators receive a virtual memory address and perform a comparison of the virtual memory address to a plurality of predetermined addresses. The memory management unit also includes logic responsive to outputs of each of the comparators to determine a physical memory address of an element within the memory array.

Fast virtual to physical memory mapping

The disclosure is directed to a computational system including a processor, cache memory accessible to the processor, and a memory management unit accessible to the processor. The processor is configured to access a virtual memory space to perform a first task and is configured to access the virtual memory space to perform a second task. The virtual memory space references first and second sets of task instructions associated with the first and second tasks, respectively. The virtual memory space references non-instruction data associated with the first task. The cache memory is configured to store the first set of task instructions and the non-instruction data. The memory management unit is configured to determine the physical memory location of the second set of task instructions. The computational system is configured to not write the first set of task instructions and the non-instruction data to a physical location beyond the cache memory.

Method and system of memory management

The disclosure is directed to a method of loading a breakpoint enabled page of a computer program into a computer readable memory. The method includes identifying a page of a computer program to be loaded into the computer readable memory and reading a breakpoint table to identify a set of breakpoints having memory addresses located within the page of the computer program prior to loading the page of the computer program. Each breakpoint has an instruction address and an instruction storage location. For each of the set of breakpoints, the method includes reading an operating instruction of the page of the computer program located at the instruction address, storing a copy of the operating instruction at the instruction storage location within the breakpoint table, and loading a trap instruction at the instruction address to replace the operating instruction in the page of the computer program to create a breakpoint enabled page of the computer program.

System and method for implementing software breakpoints

The disclosure is directed to a computational system including a processor and a memory management unit accessible to the processor. The processor is configured to access a common virtual memory space to perform a first task of a plurality of tasks and is configured to access the common virtual memory space to perform a second task of the plurality of tasks. The common virtual memory space references a first set of instructions associated with the first task and references a second set of instructions associated with the second task. The memory management unit is configured to determine a physical memory location of at least one of the first and second sets of instructions when the associated first or second task is to be performed by the processor.

The disclosure is directed to a computational device including functional circuitry, a transceiver interface that is accessible to the functional circuitry, and a universal serial bus transceiver that is accessible to the transceiver interface and that is configured to couple to a universal serial bus compatible media. The transceiver interface is configured to provide a first set of configuration data including a first power setting to a host device via the universal serial bus transceiver. The universal serial bus transceiver is configured to electrically disconnect from and electrically reconnect to the universal serial bus media in response to a suspension signal. The transceiver interface is also configured to provide a second set of configuration data including a second power setting after electrically reconnecting.

System and method for accessing universal serial bus networks

A semiconductor device includes an adjustable current source that is coupled to an external battery. The semiconductor device includes a feedback control module that is responsive to a voltage level at the external battery. The feedback control module also has an output that is directed to control the current supplied by the adjustable current source. Also, the feedback control module can selectively provide a signal to periodically and temporarily turn off the current supplied by the adjustable current source. A voltage at the external battery is measured during a time period when the current is turned on and during a time period when the current is turned off. While the current is turned off, the feedback control module can measure the external battery voltage so that it can be compared to the battery voltage while the adjustable current source is on.

System, method and semiconductor device for charging a secondary battery

A method for 'booting up' a multiple function device that involves first detecting the activation of the multiple function device. A 1boot algorithm, retrieved from read-only memory, is executed to identify the location of a 2boot algorithm. The 2boot algorithm, retrieved from a specified location based on the booting inputs, is verified for executability. When the 2boot algorithm is executable, it is executed to retrieve the functional algorithms that configure the multiple function device in the desired configuration. When the 2boot algorithm is not executable, and the multiple function device is operably coupled to a host, the correct functional algorithm or a default functional algorithm is downloaded and executed to configure the multiple function device. When an executable functional algorithm cannot be retrieved from memory or the host, the multiple function device powers down after a predetermined amount of time.

System and method to initialize a multiple function device with a multi-part boot algorithm

An internal memory uses a resource identifier and an entry point to identify which functional program from an external memory is to be loaded into one of a plurality of overlay spaces established in the internal memory. In executing a program statement, the resource identifier identifies a corresponding functional program to perform a particular functional operation and the identified functional program is then loaded into an overlay space specified by the entry point. The functional program is then executed in the overlay space.

Use of multiple overlays to import programs from external memory

A method for 'booting up' a multiple function device that first involves determining a configuration state of the multiple function device. Based on the configuration state, a functional mode is selected from a number of functional modes. A functional algorithm associated with the selected functional modes is accessed from memory. The functional algorithm is then examined to determine if the algorithm is executable. When the functional algorithm is not executable and the multiple function device is operable coupled to a host, a functional algorithm is downloaded from the host. Otherwise, the device may time-out and is powered down.

Method for initializing multifunction handheld device by downloading second boot algorithm from a coupled host if second boot algorithm in the handheld device is not executable

An internal memory uses a resource identifier to identify which functional program from an external memory is to be loaded into an overlay space of the internal memory. In executing a program statement of a main program to perform a particular functional operation without identifying a corresponding functional program, a prelude stored in a prelude space of the internal memory provides a resource identifier for the functional operation. The resource identifier identifies a corresponding functional program to perform the particular functional operation and the identified functional program is then loaded into the overlay space to be executed.

Growing community of inventors

Austin, TX, United States of America

Russell Alvin Schultz