Apple Inc.

Other

Sun Microsystems, Inc.

Oracle America, Inc.

Russell Alexader Blaine

Daniel Allen Chimene

James Michael Magee

Jeremy C Andrus

Daniel Andreas Steffen

Cyril De La Cropte De Chanterac

John Gregory Dorsey

Bryan R Hinch

Shantonu Sen

Constantin Pistol

Andrei Dorofeev

Aditya Venkataraman

Nigel R Gamble

Kevin James Van Vechten

Matthew John Byom

Umesh Suresh Vaishampayan

Simon M Douglas

Benjamin C Trumbull

Kushal Dalmia

Vishal Patel

Joseph Sokol, Jr

Roberto G Yepez

James S Ismail

Adam H Leventhal

Lionel Divyang Desai

Joseph R Auricchio

Adam C Swift

Jainam Ashokkumar Shah

Nils A Nieuwejaar

Matthew W Wright

Arnold S Liu

Benjamin H Nham

William J Kucharski

Landon J Fuller

Thomas B Duffy

Yevgen Goryachok

John K Kim-Biggs

Eric N Schrock

Edward K Pilatowicz

Giovanni M Agnoli

Brad W Simeral

Andrew W Vogan

Amit K Vyas

Arthur L Spence

Chendi Zhang

Derek R Kumar

Jacob Z Weiss

Anand Ramadurai

Christopher John Sarcone

Albert S Liu

Jacques Anthony Vidrine

Kelly B Yancey

Brent W Schorsch

Kevin R Walker

Yiqiang Nie

Tejas Arun Bahulkar

Daniel Heller

Timothy Paul Marsland

Ross Thompson

James C McIlree

Karen A Crippes

Drew A Schmitt

Andrey V Talnikov

Shachar Katz

Oliver Cozette

Olivier Cozelle

Kari E Christianson

Embodiments described herein provide techniques to manage drivers in a user space in a data processing system. One embodiment provides a data processing system configured perform operations, comprising discovering a hardware device communicatively coupled to the communication bus, launching a user space driver daemon, establishing an inter-process communication (IPC) link between a first proxy interface for the user space driver daemon and a second proxy interface for a server process in a kernel space, receiving, at the first proxy interface, an access right to enable access to a memory buffer in the kernel space, and relaying an access request for the memory buffer from the user space driver daemon via a third-party proxy interface to enable the user space driver daemon to access the memory buffer, the access request based on the access right.

Execution space agnostic device drivers

A device implementing a system for displaying an image includes a processor configured to, generate, during a first power state of a device, a data structure specifying image frames and a respective display time for each of the image frames, and retrieve, during a second power state of the device and from the data structure, an image frame based on the respective display time for the image frame. The at least one processor is further configured to display, during a third power state of the device, the retrieved image frame on a display of the device.

Power management for image display

Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

Scheduler for amp architecture with closed loop performance and thermal controller

Memory management in a data processing system can learn one or more behaviors of software processes such as daemon software processes and application processes, and based on information learned about the behaviors, the memory management can adjust how it controls memory usage in the system. For example, a memory management system can learn how software processes react (e.g. how quickly they relaunch) to memory recovery methods, such as system initiated terminations of one or more software processes that are performed to reclaim memory to increase available volatile memory, and based on information about how they react, the memory recovery methods can operate differently depending upon how the software reacted previously.

Memory management based on classification of a software process

Scheduling of work interval objects in an AMP architecture using a closed loop performance controller

Scheduler for amp architecture using a closed loop performance and thermal controller

In one embodiment, tasks executing on a data processing system can be associated with a Quality of Service (QoS) classification that is used to determine the priority values for multiple subsystems of the data processing system. The QoS classifications are propagated when tasks interact and the QoS classes are interpreted a multiple levels of the system to determine the priority values to set for the tasks. In one embodiment, one or more sensors coupled with the data processing system monitor a set of system conditions that are used in part to determine the priority values to set for a QoS class.

Quality of service classes

Scheduler for AMP architecture with closed loop performance controller using static and dynamic thread grouping

Techniques are disclosed relating to inter-process communication. In some embodiments, a kernel receives a notification of a communication to be sent from a first thread of a first application to a second thread of a second application. The kernel provides a reply port to the first thread for receiving a reply to the communication from the second thread. The kernel facilitates sending the communication from the first thread to the second thread. The kernel increases an execution priority of the second thread in response to the kernel determining that the reply port and a destination port associated with the second thread are identified in the communication. In some embodiments, the kernel creates the reply port in response to receiving the notification and, in response to detecting the reply has been communicated to the reply port, decreases the execution priority of the second thread and removes the reply port.

Execution priority management for inter-process communication

According to one embodiment, it is determined whether data stored in a compressor pool exceeds a first predetermined threshold, the compressor pool being a fixed-size memory pool maintained in a kernel of an operating system. The compressor pool stores a plurality of compressed memory pages, each memory page storing compressed data pages that can be paged out to or paged in from a persistent storage device. The compressed memory pages are associated with a plurality of processes. A memory consumption reduction action is performed to reduce memory usage, including terminating at least one of the processes to reclaim a memory space occupied by the process, in response to determining that the data stored in the compressor pool exceeds the first predetermined threshold.

Method and apparatus for managing kernel memory of data processing systems

Scheduler for amp architecture using a closed loop performance controller and deferred inter-processor interrupts

In one embodiment, an application programming interface (API) is defined that enables a thread scheduler to communicate thread information to the CPU performance controller when dispatching a thread to a processor or processor core. When dispatching a thread, the scheduler may communicate thread information including thread state information, a general 'importance' of the thread as defined by a priority level and/or quality of service (QoS) classification, a measurement of the scheduler dispatch latency for the thread, or architectural information regarding the instructions within the thread, such as whether the thread is contains 64-bit or 32-bit instructions. The performance controller can use the information provided by the scheduler to make performance control decisions for the processor cores within the system.

Scheduler and CPU performance controller cooperation

A method and an apparatus to dynamically distribute privileges among a plurality of processes are described. Each process may have attributes including a privilege to control access to processing resources. A first process may be running with a first privilege prohibited from access to a processing resource. A second process may be running with a second privilege allowed to access the processing resource. The first process may receive a request from the second process to perform a data processing task for the second process. In response, the second privilege may be dynamically transferred to the first process to allow the first process to access the processing resource. The first process may perform operations for the data processing task with the second privilege transferred from the second process.

Method and apparatus for inter process privilige transfer

Scheduler for AMP architecture with closed loop performance controller

Growing community of inventors

San Carlos, CA, United States of America

Russell Alexader Blaine