Synopsys, Inc.

Rupesh Nayak

Li Ding

Nahmsuk Oh

Peivand Tehrani

Narender Hanchate

Subramanyam Sripada

Jindrich Zejda

William Chiu-Ting Shu

Seungwhun Paik

Hushrav Mogal

Yazdan Aghaghiri

Some embodiments determine a merged timing graph for a multi-instance module (MIM), wherein each node in the merged timing graph corresponds to a pin in the MIM, and wherein each node in the merged timing graph stores timing information associated with the corresponding pins in multiple instances of the MIM in a circuit design. The embodiments can then determine an ECO for the MIM based on the merged timing graph.

Look-ahead timing prediction for multi-instance module (MIM) engineering change order (ECO)

A logic design is analyzed using static timing analysis and timing edge tracking for various nets within the logic design. Crosstalk analysis is performed on the logic design to evaluate timing impacts. To reduce pessimism of crosstalk analysis for a victim net, arrival edges are tracked for the victim net. The switching times of the aggressor net are compared to the edges of the victim net during crosstalk analysis.

Arrival edge usage in timing analysis

A method and apparatus to provide a hierarchical timing model with crosstalk consideration is provided. In one embodiment, the method comprises performing block level analysis of a circuit, in one or a plurality of iterations, and storing per iteration data. The method further comprises, in one embodiment, utilizing the per iteration data in performing top level analysis of the circuit.

Consistent hierarchical timing model with crosstalk consideration

Systems and techniques for fixing design requirement violations in a circuit design in multiple scenarios are described. During operation, a system can receive a scenario image and a multi-scenario ECO database. The scenario image can store parameter values for circuit objects in a scenario, and the multi-scenario ECO database can store a subset of parameter values for a subset of circuit objects in multiple scenarios. Next, the system can determine an engineering change order to fix one or more design requirement violations, which can involve estimating parameter values for circuit objects in multiple scenarios using parameter values stored in the scenario image and the multi-scenario ECO database.

Fixing design requirement violations in multiple multi-corner multi-mode scenarios

One embodiment of the present invention provides systems and techniques for generating a transistor-level description of a subcircuit. A user may want to simulate a subcircuit in a circuit using a transistor-level simulator, and one or more cells in the subcircuit may need to be sensitized so that the cells are in a desired state when the subcircuit is simulated. An embodiment modifies the subcircuit by inserting analog switches in front of the cells that need to be sensitized, so that the analog switches can be used to apply a sensitization sequence to the cells during the transistor-level simulation. The embodiment can then generate a transistor-level description of the modified subcircuit. Next, the transistor-level description of the subcircuit can be stored, thereby enabling the transistor-level simulator to simulate the subcircuit.

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San Ramon, CA, United States of America

Rupesh Nayak