Intel Corporation

Rupal Parikh

Krishnakanth Venkata Sistla

Andrew J Herdrich

Ankush Varma

Mark Norman Fullerton

Vivek Garg

Dean A Mulla

Nigel C Paver

Nikhil Gupta

Nazar Syed Haider

Stephen J Strazdus

Ripan Das

Mukesh Patel

Adwait Purandare

Murli Ganeshan

Yogesh Bansal

Wing K Yu

Suresh Chemudupati

Eric Dehaemer

Aman Sewani

Jianwei Liu

Nilanjan Palit

William T Maghielse

Pavithra Sampath

Anthony Jebson

Ujjwal Gupta

Deli Deng

Nikethan Shivanand Baligar

Stanley Chen

Phani Kumar Kandula

Michael Tulanowski

Timothy Yee-Kwong Kam

Stephen Paul Haake

Kailesh B Bavaria

Stephen Wang

Dorit Shapira

Shruthi Venugopal

Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Hierarchical power management apparatus and method

A synchronization interface transfers multi-bit digital data or signal between multiple clocked logic domains while maintaining data or signal integrity. When deployed in a processor-based system, in one embodiment, a plurality of data units may be received at a source location in a first clocked domain. To control writing of the plurality of data units from the source location to a target location in a second clocked domain, an enable signal may be detected. This enable signal may be synchronized with respect to the second clocked domain. Finally, in response to the synchronized enable signal, the plurality of data units may be transferred from the first clocked domain to the target location in the second clocked domain. The synchronization interface may comprise a data path to capture the multi-bit digital data or signal based on a control logic implementing a mechanism (e.g., a state machine) to synchronously transfer the data across a first and a second asynchronously clocked domains capable of receiving a first and a second clock, respectively.

Synchronizing data or signal transfer across clocked logic domains

A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.

Conditional execution of coprocessor instruction based on main processor arithmetic flags

A semiconductor device determines whether a clocking signal intended for latching an event at the designated location is absent, and if so, information about the event that occurred in the absence of the clocking signal may be provided at the another location. The semiconductor device, in one embodiment, includes first and second clock domains capable of receiving first and second clocks, respectively. When deployed in a processor-based system, one or more interrupting events may be registered. The semiconductor device further comprises an interface to capture the interrupting events based on a control logic implementing a mechanism (e.g., a state machine) capable of remembering information associated with the interrupting events that may occur when the first clock may be temporarily absent. When the first clock restarts, a register subsequently records the information associated with the interrupting events that may have occurred.

Registering events while clocking multiple domains

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Austin, TX, United States of America

Rupal Parikh