Taiwan Semiconductor Manufacturing Comp. Ltd.

Ruopeng Wang

Eric Soenen

Martin Kinyua

Alan S Roth

Alan J Drake

A voltage regulator circuit includes a comparator configured to compare whether an output voltage of the voltage regulator circuit is either equal to or less than a reference voltage; a control unit, coupled to the comparator, and configured to use a duty ratio of the output voltage to an input voltage of the control unit to estimate a time period; a first transistor, coupled to the control unit, and configured to be selectively turned on based on the estimated time period; and an inductor, coupled to the first transistor, configured to conduct an inductor current, wherein when the comparator determines that the output voltage is either equal to or less than the reference voltage, the first transistor is turned on during the estimated time period to allow the inductor current to be increased so as to accordingly increase the output voltage.

Adaptive voltage regulator

The present disclosure relates to voltage regulation techniques. In some embodiments, a voltage regulator is configured to regulate an output voltage based on a reference voltage. The voltage regulator comprises an analog-to-digital converter, an encoder, a decoder and a power stage. The analog-to-digital converter receives the reference voltage and an output voltage of the voltage regulator and provides a digital error signal. The encoder is coupled to the analog-to-digital converter output and configured to provide a multi-bit digital control signal based upon a present value of the digital error signal, a plurality of pre-determined coefficients, and a plurality of previous values of the digital error signal. The decoder is coupled to the encoder and configured to generate a plurality of control signals based on the multi-bit digital control signal. The power stage comprises a plurality of power cells which are coupled to a power supply and which receive the plurality of control signals, respectively.

Smart voltage regulation techniques

A voltage regulator circuit includes: a comparator configured to have a first input coupled to an output voltage of the voltage regulator circuit; a second input coupled to a reference voltage and an output signal; a first transistor; a second transistor, a drain of the first transistor connected to a drain of the second transistor; an inductor connected to the drain of the first transistor and the drain of the second transistor; a capacitor and a resistor connected in parallel, between the output node and a source of the second transistor; a peak-current detector unit configured to detect peak current in the inductor; a zero-crossing detector unit configured to detect a zero-crossing current in the inductor; and a control unit configured to receive a plurality of input signals including at least an input voltage and a clock signal.

A pulse width modulation (PWM) amplifier includes a first amplifier stage, a second amplifier stage, and a gain module. The first amplifier stage is configured to amplify an analog input signal in the analog and digital domains using a first pulse width modulation (PWM) generator, to provide a first stage output for coupling to a load. The gain module is configured to amplify a quantization error of the first PWM generator by a predetermined gain. The second amplifier stage is configured to spectrally shape and attenuate the amplified quantization error of the first PWM generator using a second PWM generator, to provide a second stage output for coupling to the load.

Multi-stage amplifier with pulse width modulation (PWM) noise shaping

An amplifier includes a first stage, a second stage coupled to the first stage, and a summation circuit. The first stage is configured to receive an analog input signal, convert the analog input signal to a digital signal, and output an intermediate analog output signal in response to the digital signal. The second stage is configured to output a second analog intermediate output signal based on a scaled pulse width modulation quantization error of the first stage. The summation circuit is configured to combine the first and second analog intermediate output signals to generate an amplified output signal.

Cascaded class D amplifier with improved linearity

An amplifier includes first and second stages. The first stage includes an input node for receiving an analog input signal, an analog digital converter for converting the analog input signal to a digital input signal, and a first switching circuit for outputting a first analog intermediate output signal in response to receiving a digital pulse width modulated signal that is based on the digital input signal. The second stage is configured to receive a pulse width modulation quantization error of the first stage, scale the pulse width modulation quantization error of the first stage by a gain factor to produce a scaled pulse width modulation quantization error of the first stage, and output a second analog intermediate output signal based on the scaled pulse width modulation quantization error of the first stage. A summation circuit combines the first and second analog intermediate output signals to generate an amplified output signal.

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Shanghai, China

Ruopeng Wang