Yangtze Memory Technologies Co., Ltd.

Ruo Fang Zhang

Haohao Yang

Enbo Wang

Yushi Hu

Qianbing Xu

Fushan Zhang

Qian Tao

Yong Zhang

Qianbin Xu

In a three-dimensional memory device, an interconnect structure is formed over a substrate and a first deck is formed over the interconnect structure. The first deck includes alternating first insulating layers and first word line layers, and a first channel structure extending through the first stack. The first channel structure has a first channel dielectric region and a first channel layer. The first channel dielectric region is formed along sidewalls of the first channel structure, positioned over a top surface of the interconnect structure, and in contact with the first insulating layers and the first word line layers. The first channel layer is formed along the first channel dielectric region, and includes a rounded projection that extends away from the top surface of the interconnect structure, extends outwards into the first stack at an interface of the interconnect structure, the first channel structure and the first stack.

3D NAND memory device and method of forming the same

Aspects of the disclosure provide methods for manufacturing semiconductor devices. One of the methods forms a string of transistors in a semiconductor device over a substrate of the semiconductor device. The method includes forming a first substring of transistors having a first channel structure that includes a first channel layer and a first gate dielectric structure that extend along a vertical direction over the substrate. The method includes forming a channel connector over the first substring and forming the second substring above the channel connector. The second substring has a second channel structure. The second channel structure includes the second channel layer and a second gate dielectric structure that extend along the vertical direction. The second gate dielectric structure is formed above the channel connector. The channel connector electrically couples the first channel layer and the second channel layer.

Method of fabrication thereof a multi-level vertical memory device including inter-level channel connector

A semiconductor device includes a string of transistors stacked along a vertical direction above a substrate of the semiconductor device. The string can include a first substring, a channel connector disposed above the first substring, and a second substring. The first substring includes a first channel structure having a first channel layer and a first gate dielectric structure that extend along the vertical direction. The second substring is stacked above the channel connector, and has a second channel structure that includes a second channel layer and a second gate dielectric structure that extend along the vertical direction. The channel connector, electrically coupling the first and the second channel layer, is disposed below the second gate dielectric structure to enable formation of a conductive path in a bottom region of the second channel layer. The bottom region is associated with a lowermost transistor in the second substring.

Multi-level vertical memory device including inter-level channel connector

In a memory device, a lower memory cell string is formed over a substrate to include a first channel structure, a plurality of first word line layers and first insulating layers. The first channel structure protrudes from the substrate and passes through the first word line layers and first insulating layers. An inter deck contact is formed over the lower memory cell string and connected with the first channel structure. An upper memory cell string is formed over the inter deck contact. The upper memory cell string includes a second channel structure, a plurality of second word lines and second insulating layers. The second channel structure passes through the second word lines and second insulating layers, and extends to the inter deck contact, and further extends laterally into the second insulating layers. A channel dielectric region of the second channel structure is above the inter deck contact.

Embodiments of 3D memory devices with a semiconductor plug protected by a dielectric layer and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including a plurality of interleaved conductor layers and dielectric layers on the substrate, and a memory string extending vertically through the memory stack. The memory string includes a semiconductor plug in a lower portion of the memory string, a protective dielectric layer on the semiconductor plug, and a memory film above the protective dielectric layer and along a sidewall of the memory string.

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Wuhan, China

Ruo Fang Zhang