Marvell International Limited

Marvellworld Trade Ltd.

Credo Technology Group Limited

Credo Semiconductor (hong Kong) Limited

Runsheng He

William Lo

Sehat Sutardja

Eric Janofsky

Tsin-Ho Leung

Yiqing Guo

Tak Tsui

Jiancheng Zhang

Haoli Qian

Xiaopeng Chen

Zhipei Chi

Jing Fang

Xiang Guang Feng

Hui Wang

Ping Zheng

Yi-Chun Chen

Tek Tsui

Jeffrey Choun

Kok-Wui Cheong

Chee Hoe Chu

Zhan Yu

Shuran Wei

Xike Liu

Yiging Guo

Chan Ho Yeung

Mats Oberg

Dance Wu

Ozdal Barkan

Yifei Dai

Tak-Lap Tsui

Lawrence Chi Fung Cheng

Chen Xiaopeng

Kuan Peng

Pantas Sutardja

Jamal Riani

Michael Madden

Shaoan Dai

Yat-Tung Lam

Lawrence (Chi Fung) Cheng

Kei Peng

Peiqi Xuan

YiFei Dai

Chee Hoa Chu

Integrated circuits such as multi-channel receivers may require loop inductors resistant to electromagnetic field interference. Such loop inductors may include multiple non-overlapping loops each defining a corresponding dipole, the multiple dipoles summing to zero, with at least one of said loops having unequal areas. The multiple non-overlapping loops may include: a center loop defining a central magnetic dipole; and a plurality of peripheral loops equally spaced around a perimeter of the center loop, each peripheral loop defining a peripheral magnetic dipole oriented opposite the central magnetic dipole, the plurality of peripheral loops substantially canceling a field from the central magnetic dipole. The total number of loops may be odd, with particular embodiments of three, five, and seven loop designs disclosed. Single and multi-turn embodiments are provided.

Enhanced inductors suitable for integrated multi-channel receivers

Techniques for reducing the complexity and power requirements of precompensation units, as well as equalizers, devices, and systems employing such techniques. In an illustrative method for providing high speed equalization, the method comprises: obtaining a channel response that presents trailing intersymbol interference in a signal having a sequence of symbols from a symbol set; determining a distribution of threshold values for a precompensation unit corresponding to said channel response with said symbol set; deriving a reduced set of threshold values from said distribution; and implementing a decision feedback equalizer with a reduced-complexity precompensation unit employing the reduced set of threshold values. In a related illustrative method for providing high speed equalization, the method comprises: obtaining a channel response that presents trailing intersymbol interference in a signal having a sequence of symbols from a symbol set, the channel response and symbol set corresponding to an initial distribution of threshold values for a precompensation unit; deriving a filter that converts the channel response into a modified channel response, the modified channel response and symbol set corresponding to an improved distribution of threshold values in that the improved distribution includes fewer distinct threshold values or reduced spacing between at least some adjacent threshold values; and implementing a decision feedback equalizer with a reduced-complexity precompensation unit employing the threshold values in the improved distribution.

Reduced complexity precomputation for decision feedback equalizer

A multichannel receiver includes multiple receiver modules, each having: a voltage-controlled oscillator that generates a clock signal with a controllable frequency; a phase interpolator that applies a controllable phase shift to the clock signal to provide a sampling signal; a sampling element that produces a digital receive signal by sampling an analog receive signal in accordance with the sampling signal; a timing error estimator that operates on the digital receive signal to provide timing error estimates; a phase control filter that derives, from the timing error estimates, a phase control signal supplied to the phase interpolator, wherein the phase control signal minimizes a phase error between the sampling signal and the analog receive signal; and a frequency control filter that derives, from the timing error estimates, a frequency control signal for controlling the clock signal frequency, wherein the frequency control signal minimizes a frequency offset between the clock signal and the analog receive signal.

Integrated multi-channel receiver having independent clock recovery modules with enhanced inductors

In some implementations, an apparatus includes an echo canceller that generates an echo interference compensation signal that compensates for an echo interference signal in a communication signal, a crosstalk canceller that generates a crosstalk interference compensation signal that compensates for a crosstalk interference signal in the communication signal, and a combiner that generates a combined interference compensation signal based on the echo interference compensation signal and the crosstalk interference compensation signal.

Interference signal compensation

A system including a processor that receives a first digital signal corresponding to a first signal received by the system, and a second digital signal corresponding to a second signal transmitted by the system; generates a first control signal based on the first and second digital signals; and generates a first output signal based on the first control signal and a second analog signal corresponding to the second signal. A cancellation device generates a second control signal based on a first analog signal corresponding to the first signal, and a third control signal based on the first control signal and the first output signal; selects the second or third control signal when the system operates in a first or a second mode; and outputs a second output signal to cancel interference in the first signal according to the second analog signal and one of the second and third control signals.

Adaptive analog echo/next cancellation

A communication device including circuitry configured to receive a signal transmitted to the communication device via a communication channel. A receiver is configured to generate a filter coefficient to be used for filtering the received signal, generate a gain coefficient, wherein the gain coefficient corresponds to a condition of the communication channel, adjust the filter coefficient using the gain coefficient, and filter the received signal using the filter coefficient, as adjusted using the gain coefficient, to remove intersymbol interference from the received signal.

Systems and methods for filtering a received signal to remove intersymbol interference

A system and method of determining an unbalanced current condition in Power over Ethernet applications are disclosed. In some implementations, a user or network administrator may be notified of potential impairments due to unbalanced current.

Determining power over ethernet impairment

A receiver including recovery, error, and control modules. The recovery module: receives a data signal and an offset value; based on a coefficient, equalizes the data signal to generate an equalized signal; and generates a recovered signal based on the equalized signal. The recovered signal includes data recovered by the recovery module. The error module generates an error value based on a difference between the equalized signal and a threshold. The control module, based on the offset value, the recovered signal, and the error value: generates the coefficient; determines the threshold; and determines a characteristic of an eye diagram of the recovered signal. The recovered signal has a non-repeating pattern such that overlaid traces of the recovered signal are in a shape of an eye and provide the eye diagram. The overlaid traces include jitter. The control module generates the coefficient to reduce an amount of the jitter.

Method and apparatus for reducing jitter in overlaid traces of an eye diagram of a recovered signal generated based on a received data signal

A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design suitable for equalizing receive signals with bit rates above 10 GHz, making it feasible to employ decision feedback equalization in silicon-based optical transceiver modules. One illustrative embodiment includes a front end filter to reduce leading intersymbol interference in a receive signal; a serial-to-parallel converter and at least one pre-compensation unit that together convert the filtered signal into grouped sets of tentative decisions, the sets in each group being made available in parallel; a set of pipelined DFE multiplexer units to select a contingent symbol decision from each set of tentative decisions to form groups of contingent symbol decisions based on a presumed sequence of preceding symbol decisions; and an output multiplexer that chooses, based on preceding symbol decisions, one of said groups of contingent symbol decisions.

High-speed parallel decision feedback equalizer

A transceiver including an equalizer and a control circuit. The equalizer receives an input signal and first coefficients. The equalizer includes taps that, based on the first coefficients, filter the input signal to generate an output signal. The taps include a precursor tap, a unity tap and postcursor taps. The control circuit selects the first coefficients such that a sum of the first coefficients is equal to a predetermined value. The first coefficients include a precursor coefficient, a second coefficient, and post cursor coefficients corresponding respectively to the precursor tap, the unity tap, and the postcursor taps. The control circuit: maintains the second coefficient at a fixed value; based on the second coefficient, selects the precursor coefficient and the postcursor coefficients; and while maintaining the second coefficient at the fixed value and while the equalizer is receiving the input signal, adjusts the precursor coefficient or one of the postcursor coefficients.

Transceiver with single coefficient based equalizer taps

Circuits, architectures, methods, algorithms, software, and systems for increasing reliability of data communications using time diversity coding are disclosed. An association circuit is configured to associate a first reliability factor with a first copy of the communicated data and a second reliability factor with a second copy of the communicated data, wherein the first reliability factor is different from the second reliability factor and has a value that is a predetermined function of a known characteristic of the data communications channel at a time that the communicated data passed through the channel. A decoder is configured to recover a reliable value for the communicated data from the first copy, second copy, first reliability factor, and second reliability factor.

Circuits, architectures, methods, algorithms, software, and systems for improving the reliability of data communications having time-dependent fluctuations

A compensator generating a compensation signal to compensate for nonlinear echo in an output of a current source. The nonlinear echo is a result of transitioning the current source between an ON state and an OFF state. The compensator includes driving, weighting, function, and compensating circuits. The driving circuit receives a first signal that is based on the output of the current source. The weighting circuit is configured to generate a second signal based on weighted versions of the first signal. The function circuit, based on the second signal, (i) updates each of multiple functions, and (ii) selects a first function. The driving circuit generates a driving signal based on the first function selected by the function circuit. The compensating circuit generates the compensation signal based on the driving signal to compensate for the nonlinear echo provided by the output of the current source.

Method and apparatus to compensate for nonlinear echo in an output of a current source

Methods, software, receivers and systems for communicating information over a cyclostationary channel. The method generally includes interleaving sections of a control sequence with bits of the information. The software and receivers are generally configured to implement one or more aspects of the methods disclosed herein, and the systems generally include those that embody the inventive receivers disclosed herein. The present invention is particularly useful in powerline channels, where certain parameters (such as noise) have time-dependent or periodic variations in value. By distributing the control sequence, the incidence of carrier recovery is reduced, the likelihood of successful packet or frame transmissions is increased, and data may be more reliably communicated.

Methods, algorithms, software, circuits, architectures, and systems for improved communications over cyclostationary channels

A physical layer device configured to interface with a plurality of pairs of wires. The physical layer device includes a cable test module configured to transmit a pulse over the plurality of pairs of wires, measure a reflection of the pulse as received from the plurality of pairs of wires, and determine whether a short circuit exists in one of the plurality of pairs of wires based on the measure of the reflection of the pulse. An autonegotiation module is configured to perform autonegotiation to establish a link at a particular speed over the plurality of pairs of wires. The particular speed at which the link is established over the plurality of pairs of wires is based, at least in part, on whether a short circuit exists in one of the plurality of pairs of wires as determined by the cable test module.

Cable tester

Growing community of inventors

Sunnyvale, CA, United States of America

Runsheng He