Nec USA, Inc.

Nec Corporation

Ruixue Fan

Gopalakrishnan Ramamurthy

Brian L Mark

Alexander T Ishii

Ting Wang

Stephen B Weinstein

Rauf Izmailov

Qiang Ren

Gopalakrishan Ramamurthy

Aleksandra Smiljani&cacute;

Brian Mark

Hierarchical hybrid optical networking is based on balancing cost and performance of optical networks by providing transparent (optical) switching of subsets of wavelengths in addition to opaque (electrical) switching of individual light paths. Effective use of wavelength-subset switching requires aggregating and deaggregating wavelength subsets in a simple, cost-effective manner. Non-uniform wavebands are introduced and analyzed their performance advantage as compared with uniform wavebands. Also proposed are several architectural options for a hierarchical hybrid optical cross-connect system that combines non-uniform wavebands and improved utilization of OEO ports.

Non-uniform optical waveband aggregator and deaggregator and hierarchical hybrid optical cross-connect system

A novel protocol for scheduling of packets in high-speed cell based switches is provided. The switch is assumed to use a logical cross-bar fabric with input buffers. The scheduler may be used in optical as well as electronic switches with terabit capacity. The proposed round-robin greedy scheduling (RRGS) achieves optimal scheduling at terabit throughput, using a pipeline technique. The pipeline approach avoids the need for internal speedup of the switching fabric to achieve high utilization. A method for determining a time slot in a N&times;N crossbar switch for a round robin greedy scheduling protocol, comprising N logical queues corresponding to N output ports, the input for the protocol being a state of all the input-output queues, output of the protocol being a schedule, the method comprising: choosing input corresponding to i&equals;(constant-k&minus;1)mod N, stopping if there are no more inputs, otherwise choosing the next input in a round robin fashion determined by i&equals;(i&plus;1)mod N; choosing an output j such that a pair (i,j) to a set C&equals;&lcub;(i,j)&verbar; there is at least one packet from I to j&rcub;, if the pair (i,j) exists; removing i from a set of inputs and repeating the steps if the pair (i,j) does not exist; removing i from the set of inputs and j from a set of outputs; and adding the pair (i,j) to the schedule and repeating the steps.

RRGS-round-robin greedy scheduling for input/output terabit switches

A buffer management scheme for an ATM switch where the static and dynamic thresholds are applied appropriately at different levels to ensure efficient and fair usage of buffer memory. A novel dynamic threshold mechanism which, while ensuring fair sharing of memory, maximizes the overall memory utilization. An ATM switch using a dynamic queue threshold scheme, said ATM switch comprising K output port queues and a buffer of B cells sharing said K output port queues, wherein a common threshold is dynamically set for the K output port queues, the common threshold being changed to a new value from an old value when a new cell arrives at any of said K output queues, said new value being a maximum of a length of said any of said K output queues plus one and said old value when total queue length is less than a preset value times B and, said new value being a maximum of a said old value minus one and a statically set minimum buffer threshold when total queue length is greater than or equal to a preset value times B, wherein said preset value is greater than or equal to 0.

Optimal buffer management scheme with dynamic queue length thresholds for ATM switches

A Dynamic Rate Control (DRC) scheduler for scheduling cells for service in a generic Asynchronous Transfer Mode (ATM) switch is disclosed. According to the inventive DRC, each traffic stream associated with an internal switch queue is rate-shaped according to a rate which consists of a minimum guaranteed rate and a dynamic component computed based on congestion information within the switch. While achieving high utilization, DRC guarantees a minimum throughput for each stream and fairly distributes unused bandwidth. The distribution of unused bandwidth in DRC can be assigned flexibly, i.e., the unused bandwidth need not be shared in proportion to the minimum throughput guarantees, as in weighted fair share schedulers. Moreover, an effective closed-loop QoS control can be built into DRC by dynamically updating a set of weights based on observed QoS. Another salient feature of DRC is its ability to control congestion internal congestion at bottleneck points within a multistage switch. DRC can also be extended beyond the local switch in a hop-by-hop fashion.

Dynamic rate control scheduler for ATM networks

A flexible and scalable architecture and method that implements dynamic rate control scheduling in an ATM switch. The scheduler shapes a large number of streams according to rate values computed dynamically based on switch congestion information. To handle a large range of bit rates, a plurality of timewheels are employed with different time granularities. The streams are assigned dynamically to the timewheels based on computed rate values. The shaper architecture and method support priority levels for arbitrating among streams which are simultaneously eligible to transmit.

Time-based scheduler architecture and method for ATM networks

A large capacity ATM core switch architecture is disclosed, which supports multiple traffic classes and quality-of-service (QoS) guarantees. The switch supports both real-time traffic classes with strict QoS requirements, e.g., CBR and VBR, and non-real-time traffic classes with less stringent requirements, e.g., ABR and UBR. The architecture also accommodates real-time and non-real-time multicast flows in an efficient manner. The switch consists of a high-speed core module that interconnects input/output modules with large buffers and intelligent scheduling/buffer management mechanisms. The scheduling can be implemented using a novel dynamic rate control, which controls internal congestion and achieves fair throughput performance among competing flows at switch bottlenecks. In the dynamic rate control scheme, flows are rate-controlled according to congestion information observed at bottleneck points within the switch. Each switch flow is guaranteed a minimum service rate plus a dynamic rate component which distributes any unused bandwidth in a fair manner.

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Cranbury, NJ, United States of America

Ruixue Fan